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[Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction |
Date: |
Mon, 11 Feb 2019 15:52:40 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
v2: Update to 00eac5.
Merge choose_random_nonexcluded_tag into helper_irg since
that pseudo function no longer exists separately.
---
target/arm/helper-a64.h | 1 +
target/arm/mte_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 7 +++++
3 files changed, 65 insertions(+)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index c88797a922..0f6e78c77e 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -105,3 +105,4 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_2(mte_check1, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_3(mte_check2, TCG_CALL_NO_WG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index bcd82a9be0..cd04e4954b 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -37,6 +37,31 @@ static int allocation_tag_from_addr(uint64_t ptr)
return extract64(ptr, 56, 4);
}
+static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)
+{
+ if (exclude == 0xffff) {
+ return 0;
+ }
+ if (offset == 0) {
+ while (exclude & (1 << tag)) {
+ tag = (tag + 1) & 15;
+ }
+ } else {
+ do {
+ do {
+ tag = (tag + 1) & 15;
+ } while (exclude & (1 << tag));
+ } while (--offset > 0);
+ }
+ return tag;
+}
+
+static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
+{
+ rtag -= extract64(ptr, 55, 1);
+ return deposit64(ptr, 56, 4, rtag);
+}
+
/*
* Perform a checked access for MTE.
* On arrival, TBI is known to enabled, as is allocation_tag_access_enabled.
@@ -131,3 +156,35 @@ uint64_t HELPER(mte_check2)(CPUARMState *env, uint64_t
dirty_ptr, uint32_t tbi)
return dirty_ptr;
}
}
+
+uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
+{
+ int el = arm_current_el(env);
+ uint64_t sctlr = arm_sctlr(env, el);
+ int rtag = 0;
+
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
+ /*
+ * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if
+ * GCR_EL1.RRND==0, always producing deterministic results.
+ */
+ uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16);
+ int start = extract32(env->cp15.rgsr_el1, 0, 4);
+ int seed = extract32(env->cp15.rgsr_el1, 8, 16);
+ int offset, i;
+
+ /* RandomTag */
+ for (i = offset = 0; i < 4; ++i) {
+ /* NextRandomTagBit */
+ int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^
+ extract32(seed, 2, 1) ^ extract32(seed, 0, 1));
+ seed = (top << 15) | (seed >> 1);
+ offset |= top << i;
+ }
+ rtag = choose_nonexcluded_tag(start, offset, exclude);
+
+ env->cp15.rgsr_el1 = rtag | (seed << 8);
+ }
+
+ return address_with_allocation_tag(rn, rtag);
+}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 27ceea66d1..141a03a88f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5133,6 +5133,13 @@ static void disas_data_proc_2src(DisasContext *s,
uint32_t insn)
case 3: /* SDIV */
handle_div(s, true, sf, rm, rn, rd);
break;
+ case 4: /* IRG */
+ if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ }
+ gen_helper_irg(cpu_reg_sp(s, rd), cpu_env,
+ cpu_reg_sp(s, rn), cpu_reg(s, rm));
+ break;
case 8: /* LSLV */
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
break;
--
2.17.2
- [Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes, (continued)
- [Qemu-devel] [PATCH v3 18/28] target/arm: Implement the access tag cache flushes, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 19/28] target/arm: Clean address for DC ZVA, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 07/28] target/arm: Assert no manual change to CACHED_PSTATE_BITS, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 12/28] target/arm: Implement the GMI instruction, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 15/28] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 06/28] target/arm: Add MTE system registers, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 16/28] target/arm: Implement the STGP instruction, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 17/28] target/arm: Implement the LDGM and STGM instructions, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 09/28] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 23/28] target/arm: Cache the Tagged bit for a page in MemTxAttrs, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 10/28] target/arm: Implement the IRG instruction,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 20/28] target/arm: Implement data cache set allocation tags, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 08/28] target/arm: Add helper_mte_check{1, 2}, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 13/28] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 27/28] target/arm: Enable MTE, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 14/28] target/arm: Define arm_cpu_do_unaligned_access for CONFIG_USER_ONLY, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 21/28] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 25/28] target/arm: Add allocation tag storage for user mode, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 26/28] target/arm: Add allocation tag storage for system mode, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 22/28] tcg: Introduce target-specific page data for user-only, Richard Henderson, 2019/02/11
- [Qemu-devel] [PATCH v3 24/28] target/arm: Create tagged ram when MTE is enabled, Richard Henderson, 2019/02/11