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[Qemu-devel] [PATCH v3 09/12] target/arm: Fix set of bits kept in xregs[
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 09/12] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] |
Date: |
Fri, 8 Feb 2019 19:38:44 -0800 |
Given that we mask bits properly on set, there is no reason
to mask them again on get. We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get. Except in the (probably normal) case in which
the set clears all of the bits.
Simplify the code in set to also clear the RES0 bits.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 51be3fa16f..af22274bd9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12588,7 +12588,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
int i;
uint32_t fpscr;
- fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
+ fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
| (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
@@ -12630,7 +12630,7 @@ static inline int vfp_exceptbits_to_host(int
target_bits)
void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
{
int i;
- uint32_t changed;
+ uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
@@ -12639,12 +12639,13 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t
val)
/*
* We don't implement trapped exception handling, so the
- * trap enable bits are all RAZ/WI (not RES0!)
+ * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
+ *
+ * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
+ * (which are stored in fp_status), and the other RES0 bits
+ * in between, then we clear all of the low 16 bits.
*/
- val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE);
-
- changed = env->vfp.xregs[ARM_VFP_FPSCR];
- env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
+ env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000;
env->vfp.vec_len = (val >> 16) & 7;
env->vfp.vec_stride = (val >> 20) & 3;
--
2.17.2
- [Qemu-devel] [PATCH v3 00/12] target/arm: tcg vector cleanups, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 01/12] target/arm: Rely on optimization within tcg_gen_gvec_or, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 03/12] target/arm: Use vector minmax expanders for aarch32, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 02/12] target/arm: Use vector minmax expanders for aarch64, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 04/12] target/arm: Use tcg integer min/max primitives for neon, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 05/12] target/arm: Remove neon min/max helpers, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 07/12] target/arm: Fix arm_cpu_dump_state vs FPSCR, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 06/12] target/arm: Fix vfp_gdb_get/set_reg vs FPSCR, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 08/12] target/arm: Split out flags setting from vfp compares, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 11/12] target/arm: Use vector operations for saturation, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 09/12] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR],
Richard Henderson <=
- [Qemu-devel] [PATCH v3 10/12] target/arm: Split out FPSCR.QC to a vector field, Richard Henderson, 2019/02/08
- [Qemu-devel] [PATCH v3 12/12] target/arm: Add missing clear_tail calls, Richard Henderson, 2019/02/08
- Re: [Qemu-devel] [PATCH v3 00/12] target/arm: tcg vector cleanups, no-reply, 2019/02/08
- Re: [Qemu-devel] [PATCH v3 00/12] target/arm: tcg vector cleanups, no-reply, 2019/02/08
- Re: [Qemu-devel] [PATCH v3 00/12] target/arm: tcg vector cleanups, Peter Maydell, 2019/02/14