Re: [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry

[Peter Maydell]

On Mon, 14 Jan 2019 at 01:12, Richard Henderson
<address@hidden> wrote:
>
> R0085 specifies that exception handlers begin with tag checks overridden.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index df43deb0f8..1e9ccf0b2e 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
>      qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
>                    env->elr_el[new_el]);
>
> -    pstate_write(env, PSTATE_DAIF | new_mode);
> +    pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode);
>      env->aarch64 = 1;
>      aarch64_restore_sp(env, new_el);

PSTATE_TCO being set doesn't affect codegen for non-MTE CPUs,
right?

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM