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Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
From: |
Bastian Koppelmann |
Subject: |
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree |
Date: |
Sat, 26 Jan 2019 09:51:23 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> On Tue, 22 Jan 2019 13:38:52 PST (-0800), address@hidden wrote:
>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>>> Hi,
>>>
>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>>
>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>>> Many of the gen_* functions are called by the decode functions for
>>> 16-bit
>>> and 32-bit functions. If we move translation code from the gen_*
>>> functions to the generated trans_* functions of decode-tree, we get a
>>> lot of
>>> duplication. Therefore, we mostly generate calls to the old gen_*
>>> function
>>> which are properly replaced after step 2).
>>>
>>> Each of the trans_ functions are grouped into files corresponding to
>>> their
>>> ISA extension, e.g. addi which is in RV32I is translated in the file
>>> 'trans_rvi.inc.c'.
>>>
>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>>> All 16 bit instructions have a direct mapping to a 32 bit instruction.
>>> Thus,
>>> we convert the arguments in the 16 bit trans_ function to the arguments
>>> of
>>> the corresponding 32 bit instruction and call the 32 bit trans_
>>> function.
>>>
>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>>> this move all manual translation code into the trans_* instructions of
>>> decode tree, such that we can remove the old decode_* functions.
>>>
>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as
>>> suggested
>>> by Richard. [Patch 31-35]
>>>
>>> full tree available at
>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>>
>>> Cheers,
>>> Bastian
>>>
>>> v4 -> v5:
>>> - fixed rebase error
>>> - moved TARGET_LONG_BITS check of shift instructions before rd == 0
>>> check
>>> - removed extra sign extension of sraiw
>>> - removed rs2 == 0 special cases in sraw/srlw
>>
>> All looks good to me now. Thanks for persevering.
>
> Thanks for reviewing this.
>
> Bastian: what sort of testing have you done here? This is a pretty big
> change,
> and while it's been fairly extensively reviewed I'm just generally paranoid.
>
I ran riscv-test as well as booting the newest fedora.
Cheers,
Bastian
- [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree, (continued)
- [Qemu-devel] [PATCH v5 07/35] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 03/35] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/01/22
- [Qemu-devel] [PATCH v5 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann, 2019/01/22
- Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, Richard Henderson, 2019/01/22
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31
Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree, no-reply, 2019/01/31