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Re: [Qemu-devel] [PATCH 2/2] i386: Add some MSR based features on Cascad
From: |
Eduardo Habkost |
Subject: |
Re: [Qemu-devel] [PATCH 2/2] i386: Add some MSR based features on Cascadelake-Server CPU model |
Date: |
Mon, 14 Jan 2019 16:35:45 -0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Sorry, we do have a problem here:
On Thu, Dec 27, 2018 at 10:43:04AM +0800, Tao Xu wrote:
[...]
> #define PC_COMPAT_3_0 \
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 09706ad51a..5296c73cd5 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2499,7 +2499,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
> CPUID_7_0_ECX_AVX512VNNI,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
> + CPUID_7_0_EDX_ARCH_CAPABILITIES,
CPUID_7_0_EDX_ARCH_CAPABILITIES is still set on
unmigratable_flags. We need to make it migratable before adding
it by default to a named CPU model.
Also, why are you setting this only on Cascadelake-Server and not
on all the other Intel CPUs?
I'm queueing only patch 1/2 until we sort this out.
--
Eduardo
- Re: [Qemu-devel] [PATCH 2/2] i386: Add some MSR based features on Cascadelake-Server CPU model,
Eduardo Habkost <=