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[Qemu-devel] [PULL v2 12/44] target/mips: Support R5900 three-operand MA
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 12/44] target/mips: Support R5900 three-operand MADD and MADDU instructions |
Date: |
Mon, 31 Dec 2018 15:56:08 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
The three-operand MADD and MADDU are specific to Sony R5900 core,
and Toshiba TX19/TX39/TX79 cores as well.
The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé<address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Tested-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 58 ++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4dcab34..6c2d6fd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5033,8 +5033,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
/*
- * These MULT and MULTU instructions implemented in for example the
- * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * These MULT[U] and MADD[U] instructions implemented in for example
+ * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
* architectures are special three-operand variants with the syntax
*
* MULT[U][1] rd, rs, rt
@@ -5043,6 +5043,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
*
* (rd, LO, HI) <- rs * rt
*
+ * and
+ *
+ * MADD[U] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- (LO, HI) + rs * rt
+ *
* where the low-order 32-bits of the result is placed into both the
* GPR rd and the special register LO. The high-order 32-bits of the
* result is placed into the special register HI.
@@ -5099,8 +5107,48 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free_i32(t3);
}
break;
+ case MMI_OPC_MADD:
+ {
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t2, t0);
+ tcg_gen_ext_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_add_i64(t2, t2, t3);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ if (rd) {
+ gen_move_low32(cpu_gpr[rd], t2);
+ }
+ tcg_temp_free_i64(t2);
+ }
+ break;
+ case MMI_OPC_MADDU:
+ {
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ tcg_gen_extu_tl_i64(t2, t0);
+ tcg_gen_extu_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_add_i64(t2, t2, t3);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ if (rd) {
+ gen_move_low32(cpu_gpr[rd], t2);
+ }
+ tcg_temp_free_i64(t2);
+ }
+ break;
default:
- MIPS_INVAL("mul TXx9");
+ MIPS_INVAL("mul/madd TXx9");
generate_exception_end(ctx, EXCP_RI);
goto out;
}
@@ -27318,6 +27366,8 @@ static void decode_mmi(CPUMIPSState *env, DisasContext
*ctx)
break;
case MMI_OPC_MULT1:
case MMI_OPC_MULTU1:
+ case MMI_OPC_MADD:
+ case MMI_OPC_MADDU:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
case MMI_OPC_DIV1:
@@ -27332,8 +27382,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_MFHI1:
gen_HILO1_tx79(ctx, opc, rd);
break;
- case MMI_OPC_MADD: /* TODO: MMI_OPC_MADD */
- case MMI_OPC_MADDU: /* TODO: MMI_OPC_MADDU */
case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */
case MMI_OPC_MADD1: /* TODO: MMI_OPC_MADD1 */
case MMI_OPC_MADDU1: /* TODO: MMI_OPC_MADDU1 */
--
2.7.4
- [Qemu-devel] [PULL v2 00/44] MIPS pull request for December 2018 - v2, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 01/44] MAINTAINERS: target/mips: Add MIPS files under default-configs directory, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 07/44] target/mips: MXU: Add generic naming for optn2 constants, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 03/44] MAINTAINERS: target/mips: Reorder items alphabetically, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 14/44] disas: nanoMIPS: Fix types and format strings, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 12/44] target/mips: Support R5900 three-operand MADD and MADDU instructions,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 05/44] atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 06/44] target/mips: MXU: Add missing opcodes/decoding for LX* instructions, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 10/44] target/mips: MXU: Add handlers for max/min instructions, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 13/44] target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 02/44] MAINTAINERS: target/mips: Add filter for mips in email subjects, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 11/44] target/mips: MXU: Add handler for an align instruction, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 08/44] target/mips: MXU: Improve the comment containing MXU overview, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 04/44] MAINTAINERS: Add Aleksandar Rikalo as a reviewer for MIPS content, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 15/44] disas: nanoMIPS: Fix preamble text in nanomips.* files, Aleksandar Markovic, 2018/12/31
- [Qemu-devel] [PULL v2 16/44] disas: nanoMIPS: Remove functions that are not used, Aleksandar Markovic, 2018/12/31