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Re: [Qemu-devel] [PATCH v2 02/10] target/arm: Add HCR_EL2 bits up to ARM
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 02/10] target/arm: Add HCR_EL2 bits up to ARMv8.5 |
Date: |
Thu, 6 Dec 2018 11:15:30 +0000 |
On Mon, 3 Dec 2018 at 20:38, Richard Henderson
<address@hidden> wrote:
>
> Post v8.3 bits taken from SysReg_v85_xml-00bet8.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/cpu.h | 22 +++++++++++++++++++++-
> 1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 656a96a8f8..79d58978f7 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1249,7 +1249,7 @@ static inline void xpsr_write(CPUARMState *env,
> uint32_t val, uint32_t mask)
> #define HCR_TIDCP (1ULL << 20)
> #define HCR_TACR (1ULL << 21)
> #define HCR_TSW (1ULL << 22)
> -#define HCR_TPC (1ULL << 23)
> +#define HCR_TPCP (1ULL << 23)
We were using "TPC" here because that's what the 32-bit HCR
register names the bit; but standardizing on the 64-bit HCR_EL2
names makes sense.
thanks
-- PMM
- [Qemu-devel] [PATCH v2 00/10] target/arm: LOR, HPD, AA32HPD, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 01/10] target/arm: Move id_aa64mmfr* to ARMISARegisters, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 03/10] target/arm: Add SCR_EL3 bits up to ARMv8.5, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 02/10] target/arm: Add HCR_EL2 bits up to ARMv8.5, Richard Henderson, 2018/12/03
- Re: [Qemu-devel] [PATCH v2 02/10] target/arm: Add HCR_EL2 bits up to ARMv8.5,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 04/10] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 05/10] target/arm: Introduce arm_hcr_el2_eff, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 06/10] target/arm: Use arm_hcr_el2_eff more places, Richard Henderson, 2018/12/03