Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Logan Gunthorpe]

On 2018-11-21 11:32 a.m., Alistair Francis wrote:
> That seems like either a kernel or bbl issue.
> 
> You need to make sure that bbl doesn't edit the device tree (to add
> the Microsemi device or remove the Xilinx one) and ensure your kernel
> supports the Xilinx one.

Ok, how do I stop bbl from editing the device tree? I have a kernel with
Xilinx PCI support but it fails initializing on that machine (see below).

>> In any case, it would be nice if the Microsemi/Xilinx confusion was at
>> least explained in the commit message.
> 
> What should we say? The QEMU machine accurately models the real
> hardware which reports a Xilinx PCIe. The confusion generally appears
> above QEMU where people are used to using the MicroSemi one.

Maybe describing the bbl issue and what to do to overcome it would be
sufficient.

Logan





[    0.312000] xilinx-pcie 2000000000.pci: PCIe Link is UP
[    0.316000] xilinx-pcie 2000000000.pci: host bridge /address@hidden
ranges:
[    0.316000] xilinx-pcie 2000000000.pci:   No bus range found for
/address@hidden, using [bus 00-ff]
[    0.320000] xilinx-pcie 2000000000.pci:   MEM 0x40000000..0x5fffffff
-> 0x40000000
[    0.320000] xilinx-pcie 2000000000.pci: PCI host bridge to bus 0000:00
[    0.324000] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.324000] pci_bus 0000:00: root bus resource [mem
0x40000000-0x5fffffff]
[    0.332000] pci 0000:00:00.0: bridge configuration invalid ([bus
00-00]), reconfiguring
[    0.336000] pci_bus 0000:01: extended config space not accessible
[    0.340000] pci 0000:00:00.0: PCI bridge to [bus 01]