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[Qemu-devel] [PULL 06/16] target/arm64: properly handle DBGVR RESS bits
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/16] target/arm64: properly handle DBGVR RESS bits |
Date: |
Mon, 12 Nov 2018 17:08:06 +0000 |
From: Alex Bennée <address@hidden>
This only fails with some (broken) versions of gdb but we should
treat the top bits of DBGBVR as RESS. Properly sign extend QEMU's
reference copy of dbgbvr and also update the register descriptions in
the comment.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/kvm64.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 5de8ff0ac57..6351a54b287 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -103,7 +103,7 @@ static void kvm_arm_init_debug(CPUState *cs)
* capable of fancier matching but that will require exposing that
* fanciness to GDB's interface
*
- * D7.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers
+ * DBGBCR<n>_EL1, Debug Breakpoint Control Registers
*
* 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
* +------+------+-------+-----+----+------+-----+------+-----+---+
@@ -115,12 +115,25 @@ static void kvm_arm_init_debug(CPUState *cs)
* SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
* BAS: Byte Address Select (RES1 for AArch64)
* E: Enable bit
+ *
+ * DBGBVR<n>_EL1, Debug Breakpoint Value Registers
+ *
+ * 63 53 52 49 48 2 1 0
+ * +------+-----------+----------+-----+
+ * | RESS | VA[52:49] | VA[48:2] | 0 0 |
+ * +------+-----------+----------+-----+
+ *
+ * Depending on the addressing mode bits the top bits of the register
+ * are a sign extension of the highest applicable VA bit. Some
+ * versions of GDB don't do it correctly so we ensure they are correct
+ * here so future PC comparisons will work properly.
*/
+
static int insert_hw_breakpoint(target_ulong addr)
{
HWBreakpoint brk = {
.bcr = 0x1, /* BCR E=1, enable */
- .bvr = addr
+ .bvr = sextract64(addr, 0, 53)
};
if (cur_hw_bps >= max_hw_bps) {
--
2.19.1
- [Qemu-devel] [PULL 16/16] target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature, (continued)
- [Qemu-devel] [PULL 16/16] target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 14/16] target/arm: Correctly implement handling of HCR_EL2.{VI, VF}, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 15/16] target/arm: Hyp mode R14 is shared with User and System, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 12/16] Revert "target/arm: Implement HCR.VI and VF", Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 10/16] arm: use symbolic MDCR_TDE in arm_debug_target_el, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 13/16] target/arm: Track the state of our irq lines from the GIC explicitly, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 11/16] arm: fix aa64_generate_debug_exceptions to work with EL2, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 09/16] tests/guest-debug: fix scoping of failcount, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 07/16] target/arm64: hold BQL when calling do_interrupt(), Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 08/16] target/arm64: kvm debug set target_el when passing exception to guest, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 06/16] target/arm64: properly handle DBGVR RESS bits,
Peter Maydell <=
- [Qemu-devel] [PULL 05/16] target/arm: Fix typo in tlbi_aa64_vmalle1_write, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 04/16] hw/arm/sysbus-fdt: Only call match_fn callback if the type matches, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 03/16] MAINTAINERS: Add an entry for the 'collie' machine, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 02/16] target/arm: Remove antique TODO comment, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 01/16] target/arm: Remove workaround for small SAU regions, Peter Maydell, 2018/11/12
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/11/13