[Qemu-devel] [PULL] RISC-V Patches for the 3.1 Soft Freeze, Part 2

[Palmer Dabbelt]

The following changes since commit a2e002ff7913ce93aa0f7dbedd2123dce5f1a9cd:

  Merge remote-tracking branch 
'remotes/vivier2/tags/qemu-trivial-for-3.1-pull-request' into staging 
(2018-10-30 15:49:55 +0000)

are available in the Git repository at:

  git://github.com/riscv/riscv-qemu.git tags/riscv-for-master-3.1-sf1

for you to fetch changes up to a094b3544f2855c0489f5df3c938b14b9a5899e5:

  Add address@hidden as the RISC-V list (2018-10-30 11:04:29 -0700)

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RISC-V Patches for the 3.1 Soft Freeze, Part 2

This tag contains a few simple patches that I'd like to target for the
QEMU soft freeze.  There's only one code change: a fix to our PMP
implementation that avoids an internal truncation while computing a
partial PMP read.

I also have two updates to the MAINTAINERS file: one to add Alistair as
a RISC-V maintainer, and one to add our newly created mailing list.

----------------------------------------------------------------
Dayeol Lee (1):
      target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

Palmer Dabbelt (2):
      Add Alistair as a RISC-V Maintainer
      Add address@hidden as the RISC-V list

 MAINTAINERS        | 2 ++
 target/riscv/pmp.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)