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[Qemu-devel] [PATCH v2 11/12] disas/mips: Define R5900 disassembly const
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v2 11/12] disas/mips: Define R5900 disassembly constants |
Date: |
Thu, 1 Nov 2018 18:36:16 +0100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
disas/mips.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index d73d4094d8..9f01fda8bd 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct mips_opcode
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* Sony/Toshiba R5900 */
+#define INSN_5900 0x100000000
+
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_UNKNOWN 0 /* Gas internal use. */
@@ -646,6 +649,7 @@ struct mips_opcode
#define CPU_R5000 5000
#define CPU_VR5400 5400
#define CPU_VR5500 5500
+#define CPU_R5900 5900
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
@@ -1193,6 +1197,7 @@ extern const int bfd_mips16_num_opcodes;
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define EE INSN_5900 /* Emotion Engine */
#define G1 (T3 \
)
@@ -3861,6 +3866,7 @@ struct mips_arch_choice
#define bfd_mach_mips5000 5000
#define bfd_mach_mips5400 5400
#define bfd_mach_mips5500 5500
+#define bfd_mach_mips5900 5900
#define bfd_mach_mips6000 6000
#define bfd_mach_mips7000 7000
#define bfd_mach_mips8000 8000
@@ -3908,6 +3914,8 @@ static const struct mips_arch_choice mips_arch_choices[] =
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
--
2.18.1
- [Qemu-devel] [PATCH v2 01/12] target/mips: Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79, (continued)
- [Qemu-devel] [PATCH v2 01/12] target/mips: Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 02/12] target/mips: Generate R5900 DIV1 and DIVU1 in gen_div1_tx79, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 03/12] target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 04/12] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 05/12] target/mips: Support R5900 three-operand MADD1 and MADDU1, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 06/12] tests/tcg/mips: Test R5900 three-operand MADD, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 07/12] tests/tcg/mips: Test R5900 three-operand MADD1, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 08/12] tests/tcg/mips: Test R5900 three-operand MADDU, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 09/12] tests/tcg/mips: Test R5900 three-operand MADDU1, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 10/12] disas/mips: Increase 'member of ISAs' flag holder size, Fredrik Noring, 2018/11/01
- [Qemu-devel] [PATCH v2 11/12] disas/mips: Define R5900 disassembly constants,
Fredrik Noring <=
- [Qemu-devel] [PATCH v2 12/12] disas/mips: Disassemble R5900 DIV[U]1, M{F, T}{LO, HI}1 and MULT[U]1, Fredrik Noring, 2018/11/01