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[Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G()
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G() |
Date: |
Wed, 31 Oct 2018 14:20:24 +0100 |
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0ff3da641e..38e0ff32bb 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -590,24 +590,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
-{
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
-
- switch (op) {
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -624,8 +606,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(ctx->env, ctx);
+ gen_exception_illegal(ctx);
}
}
}
--
2.19.1
- [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, (continued)
- [Qemu-devel] [PATCH v3 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 30/35] target/riscv: Remove decode_RV32_64G(),
Bastian Koppelmann <=
- [Qemu-devel] [PATCH v3 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 11/35] target/riscv: Convert RV64A insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 13/35] target/riscv: Convert RV64F insns to decodetree, Bastian Koppelmann, 2018/10/31
- [Qemu-devel] [PATCH v3 22/35] target/riscv: Remove manual decoding from gen_load(), Bastian Koppelmann, 2018/10/31