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[Qemu-devel] [PATCH 4/4] target/arm: Install ASIDs for EL2
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 4/4] target/arm: Install ASIDs for EL2 |
Date: |
Mon, 29 Oct 2018 15:53:39 +0000 |
The VMID is the ASID for the 2nd stage page lookup.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f767467dcf..4b14f2c05b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2805,17 +2805,23 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = CPU(arm_env_get_cpu(env));
+ int vmid;
- /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
- if (raw_read(env, ri) != value) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- raw_write(env, ri, value);
- }
+ raw_write(env, ri, value);
+
+ /*
+ * TODO: with ARMv8.1-VMID16, aarch64 must examine VTCR.VS
+ * (re-evaluating with changes to VTCR) then use bits [63:48].
+ */
+ vmid = extract64(value, 48, 8);
+
+ /*
+ * A change in VMID to the stage2 page table (S2NS) invalidates
+ * the combined stage 1&2 tlbs (S12NSE1 and S12NSE0).
+ */
+ tlb_set_asid_for_mmuidx(cs, vmid, ARMMMUIdxBit_S2NS,
+ ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0);
}
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
--
2.17.2