[Qemu-devel] [PATCH v8 18/20] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR

[Aleksandar Markovic]

From: Craig Janeczek <address@hidden>

Add support for emulating the S32LDD and S32LDDR MXU instructions.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
 target/mips/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 47 insertions(+), 7 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 14e19d8..30c5721 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24414,6 +24414,52 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
     tcg_temp_free(t7);
 }
 
+/*
+ * S32LDD  XRa, Rb, S12 - Load a word from memory to XRF
+ * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte seq.
+ */
+static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
+{
+    TCGv t0, t1;
+    TCGLabel *l0;
+    uint32_t XRa, Rb, s12, sel;
+
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
+
+    l0 = gen_new_label();
+
+    XRa = extract32(ctx->opcode, 6, 4);
+    s12 = extract32(ctx->opcode, 10, 10);
+    sel = extract32(ctx->opcode, 20, 1);
+    Rb = extract32(ctx->opcode, 21, 5);
+
+    gen_load_mxu_cr(t0);
+    tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
+    tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
+
+    gen_load_gpr(t0, Rb);
+
+    tcg_gen_movi_tl(t1, s12);
+    tcg_gen_shli_tl(t1, t1, 2);
+    if (s12 & 0x200) {
+        tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
+    }
+    tcg_gen_add_tl(t1, t0, t1);
+    tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL);
+
+    if (sel == 1) {
+        /* S32LDDR */
+        tcg_gen_bswap32_tl(t1, t1);
+    }
+    gen_store_mxu_gpr(t1, XRa);
+
+    gen_set_label(l0);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+}
+
 
 /*
  * Decoding engine for MXU
@@ -24643,14 +24689,8 @@ static void decode_opc_mxu__pool04(CPUMIPSState *env, 
DisasContext *ctx)
 
     switch (opcode) {
     case OPC_MXU_S32LDD:
-        /* TODO: Implement emulation of S32LDD instruction. */
-        MIPS_INVAL("OPC_MXU_S32LDD");
-        generate_exception_end(ctx, EXCP_RI);
-        break;
     case OPC_MXU_S32LDDR:
-        /* TODO: Implement emulation of S32LDDR instruction. */
-        MIPS_INVAL("OPC_MXU_S32LDDR");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_mxu_s32ldd_s32lddr(ctx);
         break;
     default:
         MIPS_INVAL("decode_opc_mxu");
-- 
2.7.4