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[Qemu-devel] [PATCH 03/11] target/mips: Support Toshiba specific three-o
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH 03/11] target/mips: Support Toshiba specific three-operand MADD and MADDU |
Date: |
Thu, 25 Oct 2018 19:31:57 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
From: Philippe Mathieu-Daudé <address@hidden>
The three-operand MADD and MADDU are specific to the
Toshiba TX19/TX39/TX79 cores.
The "32-Bit TX System RISC TX39 Family Architecture manual"
is available at https://wiki.qemu.org/File:DSAE0022432.pdf
Signed-off-by: Philippe Mathieu-Daudé<address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Tested-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 58 +++++++++++++++++++++++++++++++++++++----
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 18167df26d..add6203c5a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4801,8 +4801,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
/*
- * These MULT and MULTU instructions implemented in for example the
- * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * These MULT[U] and MADD[U] instructions implemented in for example
+ * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
* architectures are special three-operand variants with the syntax
*
* MULT[U][1] rd, rs, rt
@@ -4811,6 +4811,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
*
* (rd, LO, HI) <- rs * rt
*
+ * and
+ *
+ * MADD[U] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- (LO, HI) + rs * rt
+ *
* where the low-order 32-bits of the result is placed into both the
* GPR rd and the special register LO. The high-order 32-bits of the
* result is placed into the special register HI.
@@ -4867,8 +4875,48 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free_i32(t3);
}
break;
+ case TX79_MMI_MADD:
+ {
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t2, t0);
+ tcg_gen_ext_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_add_i64(t2, t2, t3);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ if (rd) {
+ gen_move_low32(cpu_gpr[rd], t2);
+ }
+ tcg_temp_free_i64(t2);
+ }
+ break;
+ case TX79_MMI_MADDU:
+ {
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ tcg_gen_extu_tl_i64(t2, t0);
+ tcg_gen_extu_tl_i64(t3, t1);
+ tcg_gen_mul_i64(t2, t2, t3);
+ tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
+ tcg_gen_add_i64(t2, t2, t3);
+ tcg_temp_free_i64(t3);
+ gen_move_low32(cpu_LO[acc], t2);
+ gen_move_high32(cpu_HI[acc], t2);
+ if (rd) {
+ gen_move_low32(cpu_gpr[rd], t2);
+ }
+ tcg_temp_free_i64(t2);
+ }
+ break;
default:
- MIPS_INVAL("mul TXx9");
+ MIPS_INVAL("mul/madd TXx9");
generate_exception_end(ctx, EXCP_RI);
goto out;
}
@@ -24699,6 +24747,8 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
break;
case TX79_MMI_MULT1:
case TX79_MMI_MULTU1:
+ case TX79_MMI_MADD:
+ case TX79_MMI_MADDU:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
case TX79_MMI_DIV1:
@@ -24713,8 +24763,6 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
case TX79_MMI_MFHI1:
gen_HILO(ctx, opc, 1, rd);
break;
- case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
- case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
--
2.18.1
- [Qemu-devel] [PATCH 00/11] target/mips: Amend R5900 support, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 02/11] target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 03/11] target/mips: Support Toshiba specific three-operand MADD and MADDU,
Fredrik Noring <=
- [Qemu-devel] [PATCH 04/11] target/mips: Support R5900 three-operand MADD1 and MADDU1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 05/11] tests/tcg/mips: Test R5900 three-operand MADD, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 06/11] tests/tcg/mips: Test R5900 three-operand MADD1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 07/11] tests/tcg/mips: Test R5900 three-operand MADDU, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 08/11] tests/tcg/mips: Test R5900 three-operand MADDU1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 09/11] disas/mips: Increase 'member of ISAs' flag holder size, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 10/11] disas/mips: Define R5900 disassembly constants, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 11/11] disas/mips: Disassemble R5900 DIV[U]1, M{F, T}{LO, HI}1 and MULT[U]1, Fredrik Noring, 2018/10/25