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[Qemu-devel] [PULL v2 28/33] tests/tcg/mips: Add tests for R5900 DIV1
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 28/33] tests/tcg/mips: Add tests for R5900 DIV1 |
Date: |
Wed, 24 Oct 2018 15:40:42 +0200 |
From: Fredrik Noring <address@hidden>
Add a test for DIV1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tests/tcg/mips/mipsr5900/Makefile | 3 +-
tests/tcg/mips/mipsr5900/div1.c | 73 +++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsr5900/div1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg/mips/mipsr5900/Makefile
index 287c248..757eb83 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -8,7 +8,8 @@ SIM_FLAGS=-cpu R5900
CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
-TESTCASES = mflohi1.tst
+TESTCASES = div1.tst
+TESTCASES += mflohi1.tst
TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
TESTCASES += multu.tst
diff --git a/tests/tcg/mips/mipsr5900/div1.c b/tests/tcg/mips/mipsr5900/div1.c
new file mode 100644
index 0000000..83dafa0
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/div1.c
@@ -0,0 +1,73 @@
+/*
+ * Test R5900-specific DIV1.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+struct quotient_remainder { int32_t quotient, remainder; };
+
+static struct quotient_remainder div1(int32_t rs, int32_t rt)
+{
+ int32_t lo, hi;
+
+ __asm__ __volatile__ (
+ " div1 $0, %2, %3\n"
+ " mflo1 %0\n"
+ " mfhi1 %1\n"
+ : "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+
+ assert(rs / rt == lo);
+ assert(rs % rt == hi);
+
+ return (struct quotient_remainder) { .quotient = lo, .remainder = hi };
+}
+
+static void verify_div1(int32_t rs, int32_t rt,
+ int32_t expected_quotient,
+ int32_t expected_remainder)
+{
+ struct quotient_remainder qr = div1(rs, rt);
+
+ assert(qr.quotient == expected_quotient);
+ assert(qr.remainder == expected_remainder);
+}
+
+static void verify_div1_negations(int32_t rs, int32_t rt,
+ int32_t expected_quotient,
+ int32_t expected_remainder)
+{
+ verify_div1(rs, rt, expected_quotient, expected_remainder);
+ verify_div1(rs, -rt, -expected_quotient, expected_remainder);
+ verify_div1(-rs, rt, -expected_quotient, -expected_remainder);
+ verify_div1(-rs, -rt, expected_quotient, -expected_remainder);
+}
+
+int main()
+{
+ verify_div1_negations(0, 1, 0, 0);
+ verify_div1_negations(1, 1, 1, 0);
+ verify_div1_negations(1, 2, 0, 1);
+ verify_div1_negations(17, 19, 0, 17);
+ verify_div1_negations(19, 17, 1, 2);
+ verify_div1_negations(77773, 101, 770, 3);
+
+ verify_div1(-0x80000000, 1, -0x80000000, 0);
+
+ /*
+ * Supplementary explanation from the Toshiba TX System RISC TX79 Core
+ * Architecture manual, A-38 and B-7, https://wiki.qemu.org/File:C790.pdf
+ *
+ * Normally, when 0x80000000 (-2147483648) the signed minimum value is
+ * divided by 0xFFFFFFFF (-1), the operation will result in an overflow.
+ * However, in this instruction an overflow exception doesn't occur and
+ * the result will be as follows:
+ *
+ * Quotient is 0x80000000 (-2147483648), and remainder is 0x00000000 (0).
+ */
+ verify_div1(-0x80000000, -1, -0x80000000, 0);
+
+ return 0;
+}
--
2.7.4
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, (continued)
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 23/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 18/33] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 30/33] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 26/33] tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 22/33] tests/tcg/mips: Add tests for R5900 three-operand MULT, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 25/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 21/33] target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 15/33] target/mips: Add a placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 19/33] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 28/33] tests/tcg/mips: Add tests for R5900 DIV1,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 27/33] tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 32/33] target/mips: Fix the title of translate.c, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 33/33] target/mips: Fix decoding of ALIGN and DALIGN instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 31/33] linux-user/mips: Recognize the R5900 CPU model, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 07/33] target/mips: Define R5900 MMI2 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 10/33] target/mips: Add a placeholder for R5900 LQ, Aleksandar Markovic, 2018/10/24
- Re: [Qemu-devel] [PULL v2 00/33] MIPS queue for October 2018 - part 2 - v2, Peter Maydell, 2018/10/24