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[Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M hand
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch |
Date: |
Wed, 24 Oct 2018 14:18:40 +0200 |
From: Aleksandar Markovic <address@hidden>
Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 41 +++++++++++++++++++++++------------------
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c8c71c4..111affb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24859,6 +24859,29 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 0, 6);
+ if (opcode == OPC__MXU_MUL) {
+ uint32_t rs, rt, rd, op1;
+
+ rs = extract32(ctx->opcode, 21, 5);
+ rt = extract32(ctx->opcode, 16, 5);
+ rd = extract32(ctx->opcode, 11, 5);
+ op1 = MASK_SPECIAL2(ctx->opcode);
+
+ gen_arith(ctx, op1, rd, rs, rt);
+
+ return;
+ }
+
+ if (opcode == OPC_MXU_S32M2I) {
+ gen_mxu_s32m2i(ctx);
+ return;
+ }
+
+ if (opcode == OPC_MXU_S32I2M) {
+ gen_mxu_s32i2m(ctx);
+ return;
+ }
+
switch (opcode) {
case OPC_MXU_S32MADD:
/* TODO: Implement emulation of S32MADD instruction. */
@@ -24870,18 +24893,6 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S32MADDU");
generate_exception_end(ctx, EXCP_RI);
break;
- case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
- {
- uint32_t rs, rt, rd, op1;
-
- rs = extract32(ctx->opcode, 21, 5);
- rt = extract32(ctx->opcode, 16, 5);
- rd = extract32(ctx->opcode, 11, 5);
- op1 = MASK_SPECIAL2(ctx->opcode);
-
- gen_arith(ctx, op1, rd, rs, rt);
- }
- break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
break;
@@ -25033,12 +25044,6 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
MIPS_INVAL("OPC_MXU_S16SDI");
generate_exception_end(ctx, EXCP_RI);
break;
- case OPC_MXU_S32M2I:
- gen_mxu_s32m2i(ctx);
- break;
- case OPC_MXU_S32I2M:
- gen_mxu_s32i2m(ctx);
- break;
case OPC_MXU_D32SLL:
/* TODO: Implement emulation of D32SLL instruction. */
MIPS_INVAL("OPC_MXU_D32SLL");
--
2.7.4
- [Qemu-devel] [PATCH v7 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', (continued)
- [Qemu-devel] [PATCH v7 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 09/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 10/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 11/20] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v7 14/20] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 17/20] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 15/20] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 18/20] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/24