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[Qemu-devel] [PATCH v6 06/18] target/mips: Add bit encoding for MXU accu
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v6 06/18] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' |
Date: |
Tue, 23 Oct 2018 18:18:17 +0200 |
From: Aleksandar Markovic <address@hidden>
Add bit encoding for MXU accumulate add/subtract 1-bit pattern
'aptn1'.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ed72b32..f274ac1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23844,6 +23844,12 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
}
}
+
+/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
+#define MXU_APTN1_A 0
+#define MXU_APTN1_S 1
+
+
/*
*
* Decode MXU pool00
--
2.7.4
- [Qemu-devel] [PATCH v6 00/18] target/mips: Add limited support for Ingenic's MXU ASE, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_flags, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 04/18] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 03/18] target/mips: Amend MXU instruction opcodes, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 05/18] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 06/18] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1',
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v6 07/18] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 08/18] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 09/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 10/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 11/18] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 13/18] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 12/18] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 14/18] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 15/18] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 16/18] target/mips: Add emulation of MXU instruction D16MAC, Aleksandar Markovic, 2018/10/23