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[Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV |
Date: |
Mon, 22 Oct 2018 14:57:44 +0200 |
From: Fredrik Noring <address@hidden>
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f2aeaf4..551928d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23552,7 +23552,7 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
- INSN_LOONGSON2E | INSN_LOONGSON2F);
+ INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
@@ -26388,7 +26388,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_PREF:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ INSN_R5900);
/* Treat as NOP. */
break;
--
2.7.4
- [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class, (continued)
- [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 14/34] target/mips: Placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 24/34] tests/tcg/mips: Test R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 26/34] tests/tcg/mips: Test R5900 three-operand MULTU1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 30/34] tests/tcg/mips: Test R5900 DIVU1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 29/34] tests/tcg/mips: Test R5900 DIV1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model, Aleksandar Markovic, 2018/10/22