Re: [Qemu-devel] [PATCH] target/mips: Support Toshiba specific three-operand MADD and MADDU

[Fredrik Noring]

Hi Aleksandar,

> A peculiar case of DMULTU would be interesting.

Agreed, DMULTU would be good to test as well. (DMULTU isn't part of the
R5900 ISA, though.)

> It would be nice to implement just a single instruction from MMI, let's
> say PAND, and have a test for it.

Most if not all multimedia instructions operate on 128-bit GPRs, which
means all GPRs need to be extended. I suppose there are several ways to
implement this. The definitions in target/mips/translate.c are:

/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];

One option is to create a new array such as

static TCGv_i64 mmi_gpr[32];

that represents the upper 64 bits of each GPR. Then cpu_gpr must be of
a 64-bit type too, even when QEMU runs in 32-bit user mode. The R5900
does not implement CP0.Status.UX in hardware, though, so system mode is
64 bits, regardless.

Interestingly, LO and HI are also extended to 128 bits, where the upper
64 bits are used for the I1 pipeline instructions MULT1, etc.

Additionally, a special SA register contains the shift amount used by
the 256-bit funnel shift multimedia instruction QFSRV.

What are your thoughts on making these register extensions in QEMU?

Fredrik