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[Qemu-devel] [PULL 08/21] exec: introduce tlb_init
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 08/21] exec: introduce tlb_init |
Date: |
Tue, 16 Oct 2018 10:48:58 -0700 |
From: "Emilio G. Cota" <address@hidden>
Paves the way for the addition of a per-TLB lock.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
include/exec/exec-all.h | 8 ++++++++
accel/tcg/cputlb.c | 4 ++++
exec.c | 1 +
3 files changed, 13 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 5f78125582..815e5b1e83 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* cputlb.c */
+/**
+ * tlb_init - initialize a CPU's TLB
+ * @cpu: CPU whose TLB should be initialized
+ */
+void tlb_init(CPUState *cpu);
/**
* tlb_flush_page:
* @cpu: CPU whose TLB should be flushed
@@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
uintptr_t retaddr);
#else
+static inline void tlb_init(CPUState *cpu)
+{
+}
static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f4702ce91f..502eea2850 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) >
sizeof(run_on_cpu_data));
QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16);
#define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1)
+void tlb_init(CPUState *cpu)
+{
+}
+
/* flush_all_helper: run fn across all cpus
*
* If the wait flag is set then the src cpu's helper will be queued as
diff --git a/exec.c b/exec.c
index d0821e69aa..4fd831ef06 100644
--- a/exec.c
+++ b/exec.c
@@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
tcg_target_initialized = true;
cc->tcg_initialize();
}
+ tlb_init(cpu);
#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
--
2.17.2
- [Qemu-devel] [PULL 01/21] tcg: Implement CPU_LOG_TB_NOCHAIN during expansion, (continued)
- [Qemu-devel] [PULL 01/21] tcg: Implement CPU_LOG_TB_NOCHAIN during expansion, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 04/21] tcg: plug holes in struct TCGProfile, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 03/21] tcg: fix use of uninitialized variable under CONFIG_PROFILER, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 07/21] target/unicore32: remove tlb_flush from uc32_init_fn, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 14/21] target/arm: Convert to HAVE_CMPXCHG128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 15/21] target/arm: Check HAVE_CMPXCHG128 at translate time, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 12/21] tcg: Split CONFIG_ATOMIC128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 16/21] target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 09/21] cputlb: fix assert_cpu_is_self macro, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 13/21] target/i386: Convert to HAVE_CMPXCHG128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 08/21] exec: introduce tlb_init,
Richard Henderson <=
- [Qemu-devel] [PULL 05/21] tcg: distribute tcg_time into TCG contexts, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 06/21] target/alpha: remove tlb_flush from alpha_cpu_initfn, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 02/21] tcg: access cpu->icount_decr.u16.high with atomics, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 17/21] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 18/21] target/s390x: Split do_cdsg, do_lpq, do_stpq, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 10/21] cputlb: serialize tlb updates with env->tlb_lock, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 20/21] target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 11/21] tcg: Add tlb_index and tlb_entry helpers, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 19/21] target/s390x: Skip wout, cout helpers if op helper does not return, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 21/21] cputlb: read CPUTLBEntry.addr_write atomically, Richard Henderson, 2018/10/16