Re: [Qemu-devel] [PATCH v5 08/28] target/mips: Add CPO PWBase register

[Aleksandar Markovic]

> From: Philippe Mathieu-Daudé <address@hidden>

> > @@ -6948,6 +6969,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, 
> > int reg, int sel)
> >              tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, 
> > CP0_SegCtl2));
> >              rn = "SegCtl2";
> >              break;
> > +        case 5:
> > +            check_pw(ctx);
> > +            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, 
> > CP0_PWBase));

> Shouldn't you use gen_mfc0_load64()?

It looks to me that  tcg_gen_ld_tl() is appropriate here. It will properly 
handle endianess. There is no need for sign-extension here.

There are other 64-bit related issues wrt PWxxx registers in this patch, but 
this particular line looks OK to me.

Thanks,
Aleksandar