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Re: [Qemu-devel] [PATCH 07/10] target/arm: Implement HCR.PTW
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 07/10] target/arm: Implement HCR.PTW |
Date: |
Mon, 15 Oct 2018 08:38:13 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/12/18 7:42 AM, Peter Maydell wrote:
> If the HCR_EL2 PTW virtualizaiton configuration register bit
> is set, then this means that a stage 2 Permission fault must
> be generated if a stage 1 translation table access is made
> to an address that is mapped as Device memory in stage 2.
> Implement this.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/helper.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH 01/10] target/arm: Improve debug logging of AArch32 exception return, (continued)
- [Qemu-devel] [PATCH 03/10] target/arm: Implement HCR.FB, Peter Maydell, 2018/10/12
- [Qemu-devel] [PATCH 04/10] target/arm: Implement HCR.DC, Peter Maydell, 2018/10/12
- [Qemu-devel] [PATCH 05/10] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set, Peter Maydell, 2018/10/12
- [Qemu-devel] [PATCH 09/10] target/arm: Get IL bit correct for v7 syndrome values, Peter Maydell, 2018/10/12
- [Qemu-devel] [PATCH 07/10] target/arm: Implement HCR.PTW, Peter Maydell, 2018/10/12
- Re: [Qemu-devel] [PATCH 07/10] target/arm: Implement HCR.PTW,
Richard Henderson <=
- [Qemu-devel] [PATCH 06/10] target/arm: Implement HCR.VI and VF, Peter Maydell, 2018/10/12
- [Qemu-devel] [PATCH 08/10] target/arm: New utility function to extract EC from syndrome, Peter Maydell, 2018/10/12
- [Qemu-devel] [PATCH 10/10] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode, Peter Maydell, 2018/10/12