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Re: [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic ins
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 04/28] target/riscv: Convert RVXI arithmetic insns to decodetree |
Date: |
Fri, 12 Oct 2018 11:46:22 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> +static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
> +{
> + gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
> + return true;
> +}
> +static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
> +{
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + gen_exception_illegal(ctx);
> + return true;
> + }
> + tcg_gen_shli_tl(t, t, a->shamt);
> +
> + gen_set_gpr(a->rd, t);
> + tcg_temp_free(t);
> + } /* NOP otherwise */
> + return true;
> +}
Spacing. Any reason why trans_slli (and the other shifts) aren't using
gen_arith_imm as well?
> +static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn)
> +{
> +#if !defined(TARGET_RISCV64)
> + gen_exception_illegal(ctx);
> + return true;
> +#endif
> + gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
> + return true;
> +}
return false, like you did for trans_ld?
r~
- [Qemu-devel] [PATCH 00/28] target/riscv: Convert to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 06/28] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 05/28] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2018/10/12