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[Qemu-devel] [PATCH v2 02/12] net: cadence_gem: Announce availability of
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v2 02/12] net: cadence_gem: Announce availability of priority queues |
Date: |
Thu, 11 Oct 2018 04:19:21 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
hw/net/cadence_gem.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index e560b7a142..901c173970 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1213,6 +1213,7 @@ static void gem_reset(DeviceState *d)
int i;
CadenceGEMState *s = CADENCE_GEM(d);
const uint8_t *a;
+ uint32_t queues_mask;
DB_PRINT("\n");
@@ -1229,7 +1230,10 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF] = 0x02500111;
s->regs[GEM_DESCONF2] = 0x2ab13fff;
s->regs[GEM_DESCONF5] = 0x002f2045;
- s->regs[GEM_DESCONF6] = 0x00000200;
+ s->regs[GEM_DESCONF6] = 0x0;
+
+ queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
+ s->regs[GEM_DESCONF6] |= queues_mask;
/* Set MAC address */
a = &s->conf.macaddr.a[0];
--
2.17.1
- [Qemu-devel] [PATCH v2 00/12] arm: Add first models of Xilinx Versal SoC, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 01/12] net: cadence_gem: Disable TSU feature bit, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 02/12] net: cadence_gem: Announce availability of priority queues,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v2 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 05/12] net: cadence_gem: Add support for extended descriptors, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 04/12] net: cadence_gem: Add macro with max number of descriptor words, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 08/12] net: cadence_gem: Announce 64bit addressing support, Edgar E. Iglesias, 2018/10/10
- [Qemu-devel] [PATCH v2 10/12] target/arm: Add the Cortex-A72, Edgar E. Iglesias, 2018/10/10