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Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support
From: |
Stephen Bates |
Subject: |
Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V |
Date: |
Wed, 10 Oct 2018 13:11:04 +0000 |
User-agent: |
Microsoft-MacOutlook/10.12.0.181008 |
Andrea and Alistair
+Keith since he developed a lot of the NVMe drive model
>> Alistair Francis (5):
>> hw/riscv/virt: Increase the number of interrupts
>> hw/riscv/virt: Connect the gpex PCIe
>> riscv: Enable VGA and PCIE_VGA
>> hw/riscv/sifive_u: Connect the Xilinx PCIe
>> hw/riscv/virt: Connect a VirtIO net PCIe device
I also tried these out but I was interested in seeing if I could create NVMe
models inside the new PCIe subsystem (for both the virt and sifive_u machines).
The sifive_u machine did not work at all (so I'll leave that one for now). The
virt machine successfully mapped in the NVMe devices and the OS driver was able
to probe the nvme driver against them. However something seems to be broken
with interrupts as I see messages like these in the OS dmesg:
[ 62.852000] nvme nvme0: I/O 856 QID 1 timeout, completion polled
[ 64.832000] nvme nvme1: I/O 819 QID 1 timeout, completion polled
[ 64.836000] nvme nvme1: I/O 820 QID 1 timeout, completion polled
[ 64.840000] nvme nvme1: I/O 821 QID 1 timeout, completion polled
[ 64.844000] nvme nvme1: I/O 822 QID 1 timeout, completion polled
[ 64.848000] nvme nvme0: I/O 856 QID 1 timeout, completion polled
[ 64.852000] nvme nvme0: I/O 857 QID 1 timeout, completion polled
These imply the driver hit an admin queue timeout but when it reaped the NVMe
admin completion queue it found commands were done but no interrupt was
detected by the OS. Also on starting QEMU I see this:
bbl loader
qemu-system-riscv64: plic: invalid register write: 00002090
qemu-system-riscv64: plic: invalid register write: 00002094
qemu-system-riscv64: plic: invalid register write: 00002098
qemu-system-riscv64: plic: invalid register write: 0000209c
qemu-system-riscv64: plic: invalid register write: 000020a0
qemu-system-riscv64: plic: invalid register write: 000020a4
qemu-system-riscv64: plic: invalid register write: 000020a8
qemu-system-riscv64: plic: invalid register write: 000020ac
qemu-system-riscv64: plic: invalid register write: 000020b0
qemu-system-riscv64: plic: invalid register write: 000020b4
In pci_offset = [2080] msem = [2164] parent = [2]
My command to start qemu was:
$QEMU -nographic \
-machine virt \
-smp 1 -m 8G \
-append "console=hvc0 ro root=/dev/vda" \
-kernel $KERNEL \
-drive file=${ROOTFS},format=raw,id=hd0 \
-device virtio-blk-device,drive=hd0 \
-device virtio-net-device,netdev=net0 \
-netdev user,id=net0 \
-device nvme,drive=nvme0,serial=nvme0,cmb_size_mb=16 \
-drive file=nvme0.qcow2,if=none,id=nvme0,snapshot=on \
-drive file=nvme1.qcow2,if=none,id=nvme1,snapshot=on \
-device nvme,drive=nvme1,serial=nvme1,cmb_size_mb=64
I plan to also try with a e1000 network interface model tomorrow and see how
that behaves....
Cheers
Stephen
- [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 3/5] riscv: Enable VGA and PCIE_VGA, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/10/04
- [Qemu-devel] [PATCH v5 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device, Alistair Francis, 2018/10/04
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Andrea Bolognani, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V,
Stephen Bates <=
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Andrea Bolognani, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Stephen Bates, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Stephen Bates, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Stephen Bates, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Andrea Bolognani, 2018/10/11
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Stephen Bates, 2018/10/10
- Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair, 2018/10/10
Re: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V, Alistair, 2018/10/10