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[Qemu-devel] [PULL 7/8] softfloat: Specialize udiv_qrnnd for s390x
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 7/8] softfloat: Specialize udiv_qrnnd for s390x |
Date: |
Fri, 5 Oct 2018 13:02:00 -0500 |
The ISA has a 128/64-bit division instruction.
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
include/fpu/softfloat-macros.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
index 39eb08b4f1..eafc68932b 100644
--- a/include/fpu/softfloat-macros.h
+++ b/include/fpu/softfloat-macros.h
@@ -641,6 +641,12 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
uint64_t q;
asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
return q;
+#elif defined(__s390x__)
+ /* Need to use a TImode type to get an even register pair for DLGR. */
+ unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
+ asm("dlgr %0, %1" : "+r"(n) : "r"(d));
+ *r = n >> 64;
+ return n;
#else
uint64_t d0, d1, q0, q1, r1, r0, m;
--
2.17.1
- [Qemu-devel] [PULL 0/8] softfloat queue, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 1/8] softfloat: remove float64_trunc_to_int, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 2/8] gitmodules: add berkeley's softfloat + testfloat version 3, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 4/8] softfloat: Replace countLeadingZeros32/64 with clz32/64, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 6/8] softfloat: Specialize udiv_qrnnd for x86_64, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 8/8] softfloat: Specialize udiv_qrnnd for ppc64, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 7/8] softfloat: Specialize udiv_qrnnd for s390x,
Richard Henderson <=
- [Qemu-devel] [PULL 5/8] softfloat: Fix division, Richard Henderson, 2018/10/05
- [Qemu-devel] [PULL 3/8] tests/fp/fp-test: add floating point tests, Richard Henderson, 2018/10/05
- Re: [Qemu-devel] [PULL 0/8] softfloat queue, Peter Maydell, 2018/10/08