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Re: [Qemu-devel] [PATCH] tcg/i386: fix vector operations on 32-bit hosts
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH] tcg/i386: fix vector operations on 32-bit hosts |
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Date: |
Wed, 26 Sep 2018 09:04:26 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 8/24/18 6:17 AM, Roman Kapl wrote:
> The TCG backend uses LOWREGMASK to get the low 7 bits of register numbers.
> This
> was defined as no-op for 32-bit x86, with the assumption that we have eight
> registers anyway. This assumption is not true once we have xmm regs.
>
> Since LOWREGMASK was a no-op, xmm register indidices were wrong in opcodes and
> have overflown into other opcode fields, wreaking havoc.
>
> To trigger these problems, you can try running the "movi d8, #0x0" AArch64
> instruction on 32-bit x86. "vpxor %xmm0, %xmm0, %xmm0" should be generated,
> but instead TCG generated "vpxor %xmm0, %xmm0, %xmm2".
>
> Fixes: 770c2fc7bb ("Add vector operations")
> Signed-off-by: Roman Kapl <address@hidden>
> ---
>
> Note: It could also be possible to add a dedicated VEC_LOWREGMASK, but I don't
> think it is better or signigicantly faster.
Agreed, this does seem to be the clearest solution.
I've queued the patch with the "7" typo in the commit message fixed.
r~