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Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL
From: |
Maciej W. Rozycki |
Subject: |
Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only |
Date: |
Tue, 18 Sep 2018 19:26:50 +0100 (BST) |
User-agent: |
Alpine 2.21 (LFD 202 2017-01-01) |
Hi Fredrik,
> I agree, that is important too. I will post an updated v5 soon. Another
> alternative change is to define check_insn_opc_user_only as
>
> static inline void check_insn_opc_user_only(DisasContext *ctx, int flags)
> {
> #ifndef CONFIG_USER_ONLY
> check_insn_opc_removed(ctx, flags);
> #endif
> }
>
> by referring to check_insn_opc_removed (instead of copying its definition).
> Would you consider this an improvement for v5 too?
Yes, it does look like an improvement to me, reducing code duplication.
Thanks for looking into it further.
> > here (and swapping the two former calls ought to be fixed separately; I
> > haven't checked if there are more cases like this, but if so, then they
> > would best be amended with a single change).
>
> I'll defer other ordering and indentation fixes since I'm not sure whether
> such changes would be accepted.
Sure, no need for you to rush doing that. In the absence of someone
willing to do such clean-ups voluntarily I would consider it a
maintainer's duty really.
Maciej
- [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only, (continued)
- [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Maciej W. Rozycki, 2018/09/17
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/18
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only,
Maciej W. Rozycki <=
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/19
- Re: [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Philippe Mathieu-Daudé, 2018/09/16
Re: [Qemu-devel] [PATCH v4 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Philippe Mathieu-Daudé, 2018/09/16