[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 20/22] hw/ssi/pl022: Correct wrong DMACR and ICR
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 20/22] hw/ssi/pl022: Correct wrong DMACR and ICR handling |
Date: |
Thu, 23 Aug 2018 10:38:20 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 08/20/2018 07:11 AM, Peter Maydell wrote:
> In the PL022, register offset 0x20 is the ICR, a write-only
> interrupt-clear register. Register offset 0x24 is DMACR, the DMA
> control register. We were incorrectly implementing (a stub version
> of) DMACR at 0x20, and not implementing anything at 0x24. Fix this
> bug.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> hw/ssi/pl022.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH 17/22] hw/ssi/pl022: Don't directly call vmstate_register(), (continued)
- [Qemu-devel] [PATCH 17/22] hw/ssi/pl022: Don't directly call vmstate_register(), Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 18/22] hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 16/22] hw/ssi/pl022: Set up reset function in class init, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 20/22] hw/ssi/pl022: Correct wrong DMACR and ICR handling, Peter Maydell, 2018/08/20
- Re: [Qemu-devel] [PATCH 20/22] hw/ssi/pl022: Correct wrong DMACR and ICR handling,
Richard Henderson <=
- [Qemu-devel] [PATCH 22/22] hw/arm/mps2-tz: Fix MPS2 SCC config register values, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 21/22] hw/arm/mps2-tz: Instantiate SPI controllers, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 19/22] hw/ssi/pl022: Correct wrong value for PL022_INT_RT, Peter Maydell, 2018/08/20