Re: [Qemu-devel] [PATCH 20/22] hw/ssi/pl022: Correct wrong DMACR and ICR handling

[Richard Henderson]

On 08/20/2018 07:11 AM, Peter Maydell wrote:
> In the PL022, register offset 0x20 is the ICR, a write-only
> interrupt-clear register.  Register offset 0x24 is DMACR, the DMA
> control register.  We were incorrectly implementing (a stub version
> of) DMACR at 0x20, and not implementing anything at 0x24.  Fix this
> bug.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/ssi/pl022.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


r~