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[Qemu-devel] [PATCH v10 04/65] target/mips: Add placeholder and invocati
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v10 04/65] target/mips: Add placeholder and invocation of decode_nanomips_opc() |
Date: |
Fri, 17 Aug 2018 16:02:52 +0200 |
From: Aleksandar Markovic <address@hidden>
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4f95b9a..b71d3fe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16586,6 +16586,19 @@ enum {
NM_EVP = 0x01,
};
+
+/*
+ *
+ * nanoMIPS decoding engine
+ *
+ */
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ return 2;
+}
+
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -21402,7 +21415,10 @@ static void mips_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
int is_slot;
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
- if (!(ctx->hflags & MIPS_HFLAG_M16)) {
+ if (ctx->insn_flags & ISA_NANOMIPS32) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_nanomips_opc(env, ctx);
+ } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx);
@@ -21841,8 +21857,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Status |= (1 << CP0St_FR);
}
- if (env->CP0_Config3 & (1 << CP0C3_ISA)) {
- /* microMIPS on reset when Config3.ISA == {1, 3} */
+ if (env->CP0_Config3 & (1 << (CP0C3_ISA + 1))) {
+ /* microMIPS on reset when Config3.ISA == 3 */
env->hflags |= MIPS_HFLAG_M16;
}
--
2.7.4
- [Qemu-devel] [PATCH v10 00/65] Add nanoMIPS support to QEMU, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 01/65] target/mips: Add preprocessor constants for nanoMIPS, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 02/65] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 03/65] target/mips: Add nanoMIPS DSP ASE opcodes, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 05/65] target/mips: Add nanoMIPS decoding and extraction utilities, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 06/65] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 04/65] target/mips: Add placeholder and invocation of decode_nanomips_opc(),
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v10 11/65] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 14/65] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 10/65] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 15/65] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 28/65] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 13/65] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 17/65] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0), Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 09/65] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 07/65] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Aleksandar Markovic, 2018/08/17
- [Qemu-devel] [PATCH v10 08/65] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Aleksandar Markovic, 2018/08/17