|
| From: | Richard Henderson |
| Subject: | Re: [Qemu-devel] [PATCH v9 40/84] target/mips: Fix pre-nanoMIPS MT ASE instructions availability control |
| Date: | Thu, 16 Aug 2018 10:22:23 -0700 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 08/16/2018 10:06 AM, Aleksandar Markovic wrote: > I think some of the previously-implemented similar cases involving read-only > bits were handled the same way, and we just built on that. What would you > suggest as a more appropriate solution in such cases (of accessing "preset by > hardware" bits)? Well, ctx->insn_flags and ctx->CP0_Config1 are good examples. These are 100% read-only and fixed at cpu instantiation. I see that CP0_Config3 has one writable bit for micromips, but is fully readonly for nanomips. Therefore XNP and MT need not be copied to hflags because they will never vary. I'd suggest copying CP0_Config3 to ctx as with Config1. r~
| [Prev in Thread] | Current Thread | [Next in Thread] |