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[Qemu-devel] [PATCH v9 10/84] target/mips: Check ELPA flag only in some
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v9 10/84] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 |
Date: |
Thu, 16 Aug 2018 16:57:03 +0200 |
From: Yongbok Kim <address@hidden>
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 395368b..bdd880b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4897,12 +4897,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
{
const char *rn = "invalid";
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4913,6 +4912,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -4965,12 +4965,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
- CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -4982,6 +4981,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+ CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
2.7.4
- [Qemu-devel] [PATCH v9 00/84] Add nanoMIPS support to QEMU, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 06/84] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 05/84] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 07/84] target/mips: Add CP0 BadInstrX register, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 10/84] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v9 09/84] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 12/84] elf: Add ELF flags for MIPS machine variants, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 01/84] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 08/84] target/mips: Implement CP0 Config1.WR bit functionality, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 21/84] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 02/84] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 28/84] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PATCH v9 17/84] target/mips: Add nanoMIPS base instruction set opcodes, Aleksandar Markovic, 2018/08/16