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[Qemu-devel] [PULL 22/30] aspeed_sdmc: Handle ECC training
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/30] aspeed_sdmc: Handle ECC training |
Date: |
Thu, 16 Aug 2018 14:34:30 +0100 |
From: Joel Stanley <address@hidden>
This is required to ensure u-boot SDRAM training completes.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/misc/aspeed_sdmc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 522e01ef8c0..89de3138aff 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -27,6 +27,10 @@
#define R_STATUS1 (0x60 / 4)
#define PHY_BUSY_STATE BIT(0)
+#define R_ECC_TEST_CTRL (0x70 / 4)
+#define ECC_TEST_FINISHED BIT(12)
+#define ECC_TEST_FAIL BIT(13)
+
/*
* Configuration register Ox4 (for Aspeed AST2400 SOC)
*
@@ -148,6 +152,11 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr,
uint64_t data,
/* Will never return 'busy' */
data &= ~PHY_BUSY_STATE;
break;
+ case R_ECC_TEST_CTRL:
+ /* Always done, always happy */
+ data |= ECC_TEST_FINISHED;
+ data &= ~ECC_TEST_FAIL;
+ break;
default:
break;
}
--
2.18.0
- [Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device, (continued)
- [Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 11/30] hw/arm: make bitbanded IO optional on ARMv7-M, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 13/30] loader: extract rom_free() function, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 14/30] loader: add rom transaction API, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 16/30] Add QTest testcase for the Intel Hexadecimal, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 20/30] aspeed_sdmc: Set 'cache initial sequence' always true, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 12/30] target/arm: add "cortex-m0" CPU model, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 01/30] target/arm: Fix typo in helper_sve_ld1hss_r, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 22/30] aspeed_sdmc: Handle ECC training,
Peter Maydell <=
- [Qemu-devel] [PULL 25/30] target/arm: Ignore float_flag_input_denormal from fp_status_f16, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 17/30] imx_spi: Unset XCH when TX FIFO becomes empty, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 24/30] target/arm: Adjust FPCR_MASK for FZ16, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 23/30] aspeed: add a max_ram_size property to the memory controller, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 15/30] loader: Implement .hex file loader, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 18/30] aspeed_sdmc: Extend number of valid registers, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 19/30] aspeed_sdmc: Fix saved values, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 26/30] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 27/30] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half, Peter Maydell, 2018/08/16
- [Qemu-devel] [PULL 29/30] softfloat: Fix missing inexact for floating-point add, Peter Maydell, 2018/08/16