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Re: [Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments |
Date: |
Fri, 10 Aug 2018 02:29:11 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 08/06/2018 01:59 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <address@hidden>
>
> Mark switch fallthroughs with comments, in cases fallthroughs
> are intentional.
>
> The comments "/* fall through */" are interpreted by compilers and
> other tools, and they will not issue warnings in such cases. For gcc,
> the warning is turnend on by -Wimplicit-fallthrough. With this patch,
> there will be no such warnings in target/mips directory. If such
> warning appears in future, it should be checked if it is intentional,
> and, if yes, marked with a comment similar to those from this patch.
>
> The comment must be just before next "case", otherwise gcc won't
> understand it.
>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/mips/translate.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 051dda5..e32fd5f 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -14255,8 +14255,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
> DisasContext *ctx)
> case SDP:
> check_insn(ctx, ISA_MIPS3);
> check_mips_64(ctx);
> - /* Fallthrough */
> #endif
> + /* fall through */
> case LWP:
> case SWP:
> gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
> @@ -14266,8 +14266,8 @@ static void decode_micromips32_opc(CPUMIPSState *env,
> DisasContext *ctx)
> case SDM:
> check_insn(ctx, ISA_MIPS3);
> check_mips_64(ctx);
> - /* Fallthrough */
> #endif
> + /* fall through */
> case LWM32:
> case SWM32:
> gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
> @@ -20023,6 +20023,7 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> case OPC_MTHC1:
> check_cp1_enabled(ctx);
> check_insn(ctx, ISA_MIPS32R2);
> + /* fall through */
> case OPC_MFC1:
> case OPC_CFC1:
> case OPC_MTC1:
>
- [Qemu-devel] [PATCH v7 00/80] Add nanoMIPS support to QEMU, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 02/80] target/mips: Avoid case statements formulated by ranges, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 01/80] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments, Aleksandar Markovic, 2018/08/06
- Re: [Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v7 04/80] target/mips: Fix two instances of shadow variables, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 05/80] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 06/80] target/mips: Add CP0 BadInstrX register, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 07/80] target/mips: Add gen_op_addr_addi(), Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 08/80] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 09/80] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 10/80] elf: Remove duplicate preprocessor constant definition, Aleksandar Markovic, 2018/08/06