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[Qemu-devel] [PATCH 08/20] target/arm: Pass in current_el to fp and sve_
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 08/20] target/arm: Pass in current_el to fp and sve_exception_el |
Date: |
Wed, 8 Aug 2018 21:21:54 -0700 |
We are going to want to determine whether sve is enabled
for EL than current.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 26e9098c5f..290b1a849e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4344,12 +4344,10 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
* take care of raising that exception.
* C.f. the ARM pseudocode function CheckSVEEnabled.
*/
-static int sve_exception_el(CPUARMState *env)
+static int sve_exception_el(CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
- unsigned current_el = arm_current_el(env);
-
- if (current_el <= 1) {
+ if (el <= 1) {
bool disabled = false;
/* The CPACR.ZEN controls traps to EL1:
@@ -4360,7 +4358,7 @@ static int sve_exception_el(CPUARMState *env)
if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
disabled = true;
} else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
- disabled = current_el == 0;
+ disabled = el == 0;
}
if (disabled) {
/* route_to_el2 */
@@ -4373,7 +4371,7 @@ static int sve_exception_el(CPUARMState *env)
if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
disabled = true;
} else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
- disabled = current_el == 0;
+ disabled = el == 0;
}
if (disabled) {
return 0;
@@ -4383,7 +4381,7 @@ static int sve_exception_el(CPUARMState *env)
/* CPTR_EL2. Since TZ and TFP are positive,
* they will be zero when EL2 is not present.
*/
- if (current_el <= 2 && !arm_is_secure_below_el3(env)) {
+ if (el <= 2 && !arm_is_secure_below_el3(env)) {
if (env->cp15.cptr_el[2] & CPTR_TZ) {
return 2;
}
@@ -12318,11 +12316,10 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,
uint32_t bytes)
/* Return the exception level to which FP-disabled exceptions should
* be taken, or 0 if FP is enabled.
*/
-static inline int fp_exception_el(CPUARMState *env)
+static int fp_exception_el(CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
int fpen;
- int cur_el = arm_current_el(env);
/* CPACR and the CPTR registers don't exist before v6, so FP is
* always accessible
@@ -12385,11 +12382,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
- int fp_el = fp_exception_el(env);
+ int current_el = arm_current_el(env);
+ int fp_el = fp_exception_el(env, current_el);
uint32_t flags;
if (is_a64(env)) {
- int sve_el = sve_exception_el(env);
+ int sve_el = sve_exception_el(env, current_el);
uint32_t zcr_len;
*pc = env->pc;
@@ -12404,7 +12402,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
if (sve_el != 0 && fp_el == 0) {
zcr_len = 0;
} else {
- int current_el = arm_current_el(env);
ARMCPU *cpu = arm_env_get_cpu(env);
zcr_len = cpu->sve_max_vq - 1;
--
2.17.1
- Re: [Qemu-devel] [PATCH 03/20] target/arm: Define ID_AA64ZFR0_EL1, (continued)
- [Qemu-devel] [PATCH 02/20] target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 04/20] target/arm: Adjust sve_exception_el, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 05/20] target/arm: Fix arm_cpu_data_is_big_endian for aa64 user-only, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 06/20] target/arm: Fix arm_current_el for user-only, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 08/20] target/arm: Pass in current_el to fp and sve_exception_el,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/20] target/arm: Fix is_a64 for user-only, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 09/20] target/arm: Handle SVE vector length changes in system mode, Richard Henderson, 2018/08/09
- [Qemu-devel] [PATCH 10/20] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE, Richard Henderson, 2018/08/09