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[Qemu-devel] [PATCH v7 48/80] target/mips: Implement CP0 Config1.WR bit
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v7 48/80] target/mips: Implement CP0 Config1.WR bit functionality |
Date: |
Mon, 6 Aug 2018 19:00:15 +0200 |
From: Stefan Markovic <address@hidden>
Add testing Config1.WR bit into watch exception handling logic.
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index da03978..149b275 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5609,6 +5609,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5626,6 +5627,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6308,6 +6310,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6325,6 +6328,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7011,6 +7015,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7028,6 +7033,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -7692,6 +7698,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -7709,6 +7716,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 5:
case 6:
case 7:
+ CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
--
2.7.4
- Re: [Qemu-devel] [PATCH v7 40/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, (continued)
- [Qemu-devel] [PATCH v7 41/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 42/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 43/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 44/80] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 46/80] target/mips: Add handling of branch delay slots for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 47/80] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 48/80] target/mips: Implement CP0 Config1.WR bit functionality,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v7 49/80] target/mips: Adjust exception_resume_pc() for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 50/80] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 51/80] target/mips: Adjust set_pc() for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 52/80] target/mips: Fix ERET/ERETNC behavior related to ADEL exception, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 53/80] elf: Add nanoMIPS specific variations in ELF header fields, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 55/80] elf: Don't check FCR31_NAN2008 bit for nanoMIPS, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 54/80] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/06
- [Qemu-devel] [PATCH v7 56/80] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta, Aleksandar Markovic, 2018/08/06