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[Qemu-devel] [PATCH v6 44/77] target/mips: Add handling of branch delay
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 44/77] target/mips: Add handling of branch delay slots for nanoMIPS |
Date: |
Thu, 2 Aug 2018 16:16:31 +0200 |
From: Matthew Fortune <address@hidden>
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7e495d2..8da3fb5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1458,6 +1458,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+ bool has_isa_mode;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -4550,7 +4551,7 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
if (blink > 0) {
int post_delay = insn_bytes + delayslot_size;
- int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
+ int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
tcg_gen_movi_tl(cpu_gpr[blink],
ctx->base.pc_next + post_delay + lowbit);
@@ -11039,7 +11040,7 @@ static void gen_compute_compact_branch(DisasContext
*ctx, uint32_t opc,
int bcond_compute = 0;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
+ int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) !=
0);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
@@ -24756,6 +24757,7 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) < 3;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
--
1.9.1
- Re: [Qemu-devel] [PATCH v6 39/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, (continued)
- [Qemu-devel] [PATCH v6 40/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 41/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 42/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 43/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 44/77] target/mips: Add handling of branch delay slots for nanoMIPS,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 45/77] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 46/77] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 47/77] target/mips: Implement CP0 Config1.WR bit functionality, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 48/77] target/mips: Adjust exception_resume_pc() for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 49/77] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 50/77] target/mips: Adjust set_pc() for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 51/77] target/mips: Fix ERET/ERETNC behavior related to ADEL exception, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 52/77] elf: Add nanoMIPS specific variations in ELF header fields, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 53/77] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 54/77] elf: Don't check FCR31_NAN2008 bit for nanoMIPS, Stefan Markovic, 2018/08/02