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[Qemu-devel] [PATCH v6 34/77] target/mips: Implement emulation of nanoMI
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 34/77] target/mips: Implement emulation of nanoMIPS EXTW instruction |
Date: |
Thu, 2 Aug 2018 16:16:21 +0200 |
From: James Hogan <address@hidden>
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++----------------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 23f352a..bebdd66 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4735,8 +4735,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int rd,
int rs, int rt,
return;
}
-static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int bp)
+static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
+ int rt, int bits)
{
TCGv t0;
if (rd == 0) {
@@ -4744,35 +4744,40 @@ static void gen_align(DisasContext *ctx, int opc, int
rd, int rs, int rt,
return;
}
t0 = tcg_temp_new();
- gen_load_gpr(t0, rt);
- if (bp == 0) {
- switch (opc) {
- case OPC_ALIGN:
+ if (bits == 0 || bits == wordsz) {
+ if (bits == 0) {
+ gen_load_gpr(t0, rt);
+ } else {
+ gen_load_gpr(t0, rs);
+ }
+ switch (wordsz) {
+ case 32:
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
+ case 64:
tcg_gen_mov_tl(cpu_gpr[rd], t0);
break;
#endif
}
} else {
TCGv t1 = tcg_temp_new();
+ gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- switch (opc) {
- case OPC_ALIGN:
+ switch (wordsz) {
+ case 32:
{
TCGv_i64 t2 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t2, t1, t0);
- tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));
+ tcg_gen_shri_i64(t2, t2, 32 - bits);
gen_move_low32(cpu_gpr[rd], t2);
tcg_temp_free_i64(t2);
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
- tcg_gen_shli_tl(t0, t0, 8 * bp);
- tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));
+ case 64:
+ tcg_gen_shli_tl(t0, t0, bits);
+ tcg_gen_shri_tl(t1, t1, 64 - bits);
tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
break;
#endif
@@ -4783,6 +4788,18 @@ static void gen_align(DisasContext *ctx, int opc, int
rd, int rs, int rt,
tcg_temp_free(t0);
}
+static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int bp)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
+}
+
+static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int shift)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);
+}
+
static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
{
TCGv t0;
@@ -14245,8 +14262,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
- gen_align(ctx, OPC_ALIGN, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
@@ -17353,6 +17369,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2) - 1);
break;
+ case NM_EXTW:
+ gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
+ break;
case NM_POOL32AXF:
gen_pool32axf_nanomips_insn(env, ctx);
break;
@@ -20202,7 +20221,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
switch (op2) {
case OPC_ALIGN:
case OPC_ALIGN_END:
- gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
+ gen_align(ctx, 32, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
gen_bitswap(ctx, op2, rd, rt);
@@ -20228,7 +20247,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
switch (op2) {
case OPC_DALIGN:
case OPC_DALIGN_END:
- gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
+ gen_align(ctx, 64, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
gen_bitswap(ctx, op2, rd, rt);
--
1.9.1
- [Qemu-devel] [PATCH v6 24/77] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, (continued)
- [Qemu-devel] [PATCH v6 24/77] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 25/77] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 26/77] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 27/77] target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 28/77] target/mips: Add emulation of nanoMIPS 48-bit instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 29/77] target/mips: Add emulation of nanoMIPS FP instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 30/77] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 31/77] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 32/77] target/mips: Add emulation of misc nanoMIPS instructions (p_lsx), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 33/77] target/mips: Implement emulation of nanoMIPS ROTX instruction, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 34/77] target/mips: Implement emulation of nanoMIPS EXTW instruction,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 35/77] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 36/77] target/mips: Add emulation of nanoMIPS 32-bit branch instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 37/77] target/mips: Implement MT ASE support for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 38/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 39/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 40/77] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Stefan Markovic, 2018/08/02