Re: [Qemu-devel] [PATCH v5 48/76] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS

[Richard Henderson]

On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim <address@hidden>
> 
> Config3.ISAOnExc is read only in nanoMIPS.
> 
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
>  target/mips/op_helper.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index cb83b6d..5e10286 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -1730,7 +1730,8 @@ void helper_mtc0_config2(CPUMIPSState *env, 
> target_ulong arg1)
>  
>  void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
>  {
> -    if (env->insn_flags & ASE_MICROMIPS) {
> +    if ((env->insn_flags & ASE_MICROMIPS) &&
> +        !(env->insn_flags & ISA_NANOMIPS32)) {'

Didn't we say nanomips does not include micromips?


r~