Re: [Qemu-devel] [PATCH v5 41/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4

[Richard Henderson]

On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
 +static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
> +                                          int ret, int v1, int v2)
> +{
> +    TCGv t0;
> +    TCGv t1;
> +
> +    TCGv v0_t;
> +    TCGv v1_t;
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +
> +    v0_t = tcg_temp_new();
> +    v1_t = tcg_temp_new();
> +
> +    gen_load_gpr(v0_t, ret);
> +    gen_load_gpr(v1_t, v1);
> +
> +    switch (opc) {
> +    case NM_POOL32AXF_2_0_7:
> +        switch (extract32(ctx->opcode, 9, 3)) {
> +        case NM_DPA_W_PH:
> +        case NM_DPAQ_S_W_PH:
> +        case NM_DPS_W_PH:
> +        case NM_DPSQ_S_W_PH:
> +            gen_pool32axf_2_multiply(ctx, opc, ret, v1, v2);

This structure, in which you have loaded gpr values, then discard them only to
load them up again in a different helper function, could use some improvement.

> +        case NM_BALIGN:
> +            gen_load_gpr(t0, v1);
> +            v2 &= 3;
> +            if (v2 != 0 && v2 != 2) {
> +                tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 8 * v2);

More unprotected uses of cpu_gpr[0].


r~