Re: [Qemu-devel] [PATCH v5 40/76] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3

[Richard Henderson]

On 07/30/2018 12:12 PM, Aleksandar Markovic wrote:
> From: Stefan Markovic <address@hidden>
> 
> Add emulation of DSP ASE instructions for nanoMIPS - part 3.
> 
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
>  target/mips/translate.c | 180 
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 180 insertions(+)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 055be7e..e597b35 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -16872,13 +16872,191 @@ static void 
> gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
>      }
>  }
>  
> +/* dsp */
> +static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
> +                                            int ret, int v1, int v2)
> +{
> +    TCGv_i32 t0;
> +    TCGv v0_t;
> +    TCGv v1_t;
> +
> +    t0 = tcg_temp_new_i32();
> +
> +    v0_t = tcg_temp_new();
> +    v1_t = tcg_temp_new();
> +
> +    tcg_gen_movi_i32(t0, v2 >> 3);
> +
> +    gen_load_gpr(v0_t, ret);
> +    gen_load_gpr(v1_t, v1);
> +
> +    switch (opc) {
> +    case NM_MAQ_S_W_PHR:
> +        check_dsp(ctx);
> +        gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env);
> +        break;
> +    case NM_MAQ_S_W_PHL:
> +        check_dsp(ctx);
> +        gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env);
> +        break;
> +    case NM_MAQ_SA_W_PHR:
> +        check_dsp(ctx);
> +        gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env);
> +        break;
> +    case NM_MAQ_SA_W_PHL:
> +        check_dsp(ctx);
> +        gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
> +        break;
> +    default:
> +        generate_exception_end(ctx, EXCP_RI);
> +        break;
> +    }
> +
> +    tcg_temp_free_i32(t0);
> +
> +    tcg_temp_free(v0_t);
> +    tcg_temp_free(v1_t);
> +}
> +
> +
> +static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
> +                                    int ret, int v1, int v2)
> +{
> +    int16_t imm;
> +
> +    TCGv t0;
> +    TCGv t1;
> +    TCGv v0_t;
> +    TCGv v1_t;
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +
> +    v0_t = tcg_temp_new();
> +    v1_t = tcg_temp_new();
> +
> +    gen_load_gpr(v0_t, ret);

Did you really mean to load the result?

> +    gen_load_gpr(v1_t, v1);
> +
> +    switch (opc) {
> +    case NM_POOL32AXF_1_0:
> +        switch (extract32(ctx->opcode, 12, 2)) {
> +        case NM_MFHI:
> +            gen_HILO(ctx, OPC_MFHI, v2 >> 3, ret);
> +            break;
> +        case NM_MFLO:
> +            gen_HILO(ctx, OPC_MFLO, v2 >> 3, ret);
> +            break;

The result isn't stored.

> +    case NM_POOL32AXF_1_3:
> +        imm = extract32(ctx->opcode, 14, 7);
> +        switch (extract32(ctx->opcode, 12, 2)) {
> +        case NM_RDDSP:
> +            tcg_gen_movi_tl(t0, imm);
> +            gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env);
> +            break;

Unprotected use of cpu_gpr[0].
And many others.


r~