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[Qemu-devel] [PATCH 83/99] target/arm: Implement FCSEL for fp16
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 83/99] target/arm: Implement FCSEL for fp16 |
Date: |
Mon, 23 Jul 2018 15:17:32 -0500 |
From: Alex Bennée <address@hidden>
These were missed out from the rest of the half-precision work.
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[rth: Fix erroneous check vs type]
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
(cherry picked from commit ace97feef3613194900d4eb9ffc6819b840fbaeb)
Signed-off-by: Michael Roth <address@hidden>
---
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 05d51ecbdc..7075f27e05 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4660,15 +4660,34 @@ static void disas_fp_csel(DisasContext *s, uint32_t
insn)
unsigned int mos, type, rm, cond, rn, rd;
TCGv_i64 t_true, t_false, t_zero;
DisasCompare64 c;
+ TCGMemOp sz;
mos = extract32(insn, 29, 3);
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+ type = extract32(insn, 22, 2);
rm = extract32(insn, 16, 5);
cond = extract32(insn, 12, 4);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
- if (mos || type > 1) {
+ if (mos) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ switch (type) {
+ case 0:
+ sz = MO_32;
+ break;
+ case 1:
+ sz = MO_64;
+ break;
+ case 3:
+ sz = MO_16;
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ break;
+ }
+ /* fallthru */
+ default:
unallocated_encoding(s);
return;
}
@@ -4677,11 +4696,11 @@ static void disas_fp_csel(DisasContext *s, uint32_t
insn)
return;
}
- /* Zero extend sreg inputs to 64 bits now. */
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
t_true = tcg_temp_new_i64();
t_false = tcg_temp_new_i64();
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
+ read_vec_element(s, t_true, rn, 0, sz);
+ read_vec_element(s, t_false, rm, 0, sz);
a64_test_cc(&c, cond);
t_zero = tcg_const_i64(0);
@@ -4690,7 +4709,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(t_false);
a64_free_cc(&c);
- /* Note that sregs write back zeros to the high bits,
+ /* Note that sregs & hregs write back zeros to the high bits,
and we've already done the zero-extension. */
write_fp_dreg(s, rd, t_true);
tcg_temp_free_i64(t_true);
--
2.17.1
- [Qemu-devel] [PATCH 74/99] target/arm: Clear SVE high bits for FMOV, (continued)
- [Qemu-devel] [PATCH 74/99] target/arm: Clear SVE high bits for FMOV, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 76/99] target/arm: Implement FMOV (general) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 77/99] target/arm: Implement FCVT (scalar, integer) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 75/99] fpu/softfloat: Fix conversion from uint64 to float128, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 78/99] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 80/99] target/arm: Implement FP data-processing (2 source) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 07/99] target/arm: Implement v8M VLLDM and VLSTM, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 81/99] target/arm: Implement FP data-processing (3 source) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 84/99] target/arm: Implement FMOV (immediate) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 83/99] target/arm: Implement FCSEL for fp16,
Michael Roth <=
- [Qemu-devel] [PATCH 82/99] target/arm: Implement FCMP for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 85/99] target/arm: Fix sqrt_f16 exception raising, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 86/99] hw/isa/superio: Fix inconsistent use of Chardev->be, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 87/99] mux: fix ctrl-a b again, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 88/99] nfs: Remove processed options from QDict, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 89/99] replace functions which are only available in glib-2.24, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 90/99] vfio/pci: Default display option to "off", Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 91/99] migration/block-dirty-bitmap: fix dirty_bitmap_load, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 08/99] target/ppc: always set PPC_MEM_TLBIE in pre 2.8 migration hack, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 92/99] tcg: Reduce max TB opcode count, Michael Roth, 2018/07/23