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Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consi
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up |
Date: |
Sun, 15 Jul 2018 22:14:27 +0100 |
On 15 July 2018 at 01:37, Richard Henderson <address@hidden> wrote:
> On 07/13/2018 10:09 AM, Peter Maydell wrote:
>> @@ -939,29 +935,21 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env,
>> target_ulong addr)
>> }
>> assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>> }
>> + assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>
> Don't duplicate the assert; just move it.
Yeah, the duplicate is unwanted: I probably ended upit
from a botched conflict resolution at some point in a rebase
when I was moving it around.
> Reviewed-by: Richard Henderson <address@hidden>
thanks
-- PMM