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[Qemu-devel] [PATCH v3 4/5] i386: Add CPUID bit for WBNOINVD
From: |
Robert Hoo |
Subject: |
[Qemu-devel] [PATCH v3 4/5] i386: Add CPUID bit for WBNOINVD |
Date: |
Wed, 4 Jul 2018 17:06:38 +0800 |
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=80000008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo <address@hidden>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9407071..9ad3f93 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1027,7 +1027,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] =
{
.feat_names = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
+ NULL, "wbnoinvd", NULL, NULL,
"ibpb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 12a7e6c..265f428 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -694,6 +694,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass
Disable */
+#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
+ do not invalidate cache */
#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction
Barrier */
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
--
1.8.3.1
- [Qemu-devel] [PATCH v3 0/5] Add Icelake CPU model, Robert Hoo, 2018/07/04
- [Qemu-devel] [PATCH v3 3/5] i386: Add CPUID bit for PCONFIG, Robert Hoo, 2018/07/04
- [Qemu-devel] [PATCH v3 4/5] i386: Add CPUID bit for WBNOINVD,
Robert Hoo <=
- [Qemu-devel] [PATCH v3 5/5] i386: Add new CPU model Icelake-{Server, Client}, Robert Hoo, 2018/07/04
- [Qemu-devel] [PATCH v3 2/5] i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR, Robert Hoo, 2018/07/04
- [Qemu-devel] [PATCH v3 1/5] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES, Robert Hoo, 2018/07/04