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[Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches |
Date: |
Fri, 29 Jun 2018 15:53:10 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 21 +++++++++++++++++++++
target/arm/sve.decode | 23 +++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 11541b1a502..c73c3fc2151 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4303,3 +4303,24 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz
*a, uint32_t insn)
cpu_reg_sp(s, a->rn), fn);
return true;
}
+
+/*
+ * Prefetches
+ */
+
+static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
+{
+ /* Prefetch is a nop within QEMU. */
+ sve_access_check(s);
+ return true;
+}
+
+static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
+{
+ if (a->rm == 31) {
+ return false;
+ }
+ /* Prefetch is a nop within QEMU. */
+ sve_access_check(s);
+ return true;
+}
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 7d24c2bdc4c..80b955ff840 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -794,6 +794,29 @@ LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
@rpri_load_msz nreg=0
+# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
+PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
+
+# SVE 32-bit gather prefetch (vector plus immediate)
+PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
+
+# SVE contiguous prefetch (scalar plus immediate)
+PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
+
+# SVE contiguous prefetch (scalar plus scalar)
+PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
+
+### SVE Memory 64-bit Gather Group
+
+# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
+PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
+
+# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
+PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
+
+# SVE 64-bit gather prefetch (vector plus immediate)
+PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
+
### SVE Memory Store Group
# SVE store predicate register
--
2.17.1
- [Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning, (continued)
- [Qemu-devel] [PULL 06/55] hw/arm/virt: Silence dtc /memory warning, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 03/55] device_tree: Replace error_setg(&error_fatal) by error_report() + exit(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 02/55] hw/arm/sysbus-fdt: Replace error_setg(&error_fatal) by error_report() + exit(), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 14/55] target/arm: Implement SVE Floating Point Accumulating Reduction Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 16/55] target/arm: Implement SVE store vector/predicate register, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 07/55] target/arm: Implement SVE Memory Contiguous Load Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 21/55] target/arm: Implement SVE scatter store vector immediate, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 26/55] target/arm: Implement SVE Floating Point Unary Operations - Unpredicated Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 32/55] target/arm: Implement SVE floating-point unary operations, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 15/55] target/arm: Implement SVE load and broadcast element, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches,
Peter Maydell <=
- [Qemu-devel] [PULL 17/55] target/arm: Implement SVE scatter stores, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 20/55] target/arm: Implement SVE first-fault gather loads, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 22/55] target/arm: Implement SVE floating-point compare vectors, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 23/55] target/arm: Implement SVE floating-point arithmetic with immediate, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 25/55] target/arm: Implement SVE FP Fast Reduction Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 30/55] target/arm: Implement SVE floating-point convert to integer, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 27/55] target/arm: Implement SVE FP Compare with Zero Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 33/55] target/arm: Implement SVE MOVPRFX, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 37/55] target/arm: Implement SVE fp complex multiply add (indexed), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 19/55] target/arm: Implement SVE gather loads, Peter Maydell, 2018/06/29