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Re: [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access checks |
Date: |
Thu, 28 Jun 2018 21:48:10 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check
> produced by the flag already includes fp_access_check. If
> we also check ARM_CP_FPU the double fp_access_check asserts.
Maybe we can surround this assert() with #ifdef DEBUG_DISAS...
> Reported-by: Laurent Desnogues <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/arm/helper.c | 8 ++++----
> target/arm/translate-a64.c | 5 ++---
> 2 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index b19c7ace78..a855da045b 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4393,7 +4393,7 @@ static void zcr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static const ARMCPRegInfo zcr_el1_reginfo = {
> .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
> - .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
> + .access = PL1_RW, .type = ARM_CP_SVE,
> .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
> .writefn = zcr_write, .raw_writefn = raw_write
> };
> @@ -4401,7 +4401,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = {
> static const ARMCPRegInfo zcr_el2_reginfo = {
> .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
> - .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
> + .access = PL2_RW, .type = ARM_CP_SVE,
> .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
> .writefn = zcr_write, .raw_writefn = raw_write
> };
> @@ -4409,14 +4409,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = {
> static const ARMCPRegInfo zcr_no_el2_reginfo = {
> .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
> - .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
> + .access = PL2_RW, .type = ARM_CP_SVE,
> .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
> };
>
> static const ARMCPRegInfo zcr_el3_reginfo = {
> .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
> - .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
> + .access = PL3_RW, .type = ARM_CP_SVE,
> .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
> .writefn = zcr_write, .raw_writefn = raw_write
> };
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index f986340832..45a6c2a3aa 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t
> insn, bool isread,
> default:
> break;
> }
> - if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
> - return;
> - }
> if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
> return;
> + } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
> + return;
> }
>
> if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
>
- [Qemu-devel] [PATCH 0/6] target/arm SVE updates, Richard Henderson, 2018/06/28
- [Qemu-devel] [PATCH 1/6] target/arm: Fix SVE signed division vs x86 overflow exception, Richard Henderson, 2018/06/28
- [Qemu-devel] [PATCH 2/6] target/arm: Fix SVE system register access checks, Richard Henderson, 2018/06/28
- [Qemu-devel] [PATCH 3/6] target/arm: Prune a57 features from max, Richard Henderson, 2018/06/28
- [Qemu-devel] [PATCH 4/6] target/arm: Prune a15 features from max, Richard Henderson, 2018/06/28
- [Qemu-devel] [PATCH 5/6] target/arm: Add ID_ISAR6, Richard Henderson, 2018/06/28