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Re: [Qemu-devel] [PATCH v5 27/35] target/arm: Implement SVE MOVPRFX
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 27/35] target/arm: Implement SVE MOVPRFX |
Date: |
Tue, 26 Jun 2018 13:24:07 +0100 |
On 21 June 2018 at 02:53, Richard Henderson
<address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate-sve.c | 60 +++++++++++++++++++++++++++++++++++++-
> target/arm/sve.decode | 7 +++++
> 2 files changed, 66 insertions(+), 1 deletion(-)
> +/*
> + * Move Prefix
> + *
> + * TODO: The implementation so far could handle predicated merging movprfx.
> + * The helper functions as written take an extra source register to
> + * use in the operation, but the result is only written when predication
> + * succeeds. For unpredicated movprfx, we need to rearrange the helpers
> + * to allow the final write back to the destination to be unconditional.
> + * For predicated zering movprfz, we need to rearrange the helpers to
"zeroing". Should that be "movprfx" or is "movprfz" a thing? (the SVE
spec doesn't mention it.)
> + * allow the final write back to zero inactives.
> + *
> + * In the meantime, just emit the moves.
> + */
> +
> +static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a, uint32_t insn)
> +{
> + return do_mov_z(s, a->rd, a->rn);
> +}
A bit confusing that do_mov_z() does the sve_access_check() for us
but do_sel_z() and do_movz_zpz() do not...
> +
> +static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> +{
> + if (sve_access_check(s)) {
> + do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
> + }
> + return true;
> +}
> +
> +static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
> +{
> + if (sve_access_check(s)) {
> + do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);
> + }
> + return true;
> +}
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v5 22/35] target/arm: Implement SVE floating-point trig multiply-add coefficient, (continued)
- [Qemu-devel] [PATCH v5 21/35] target/arm: Implement SVE FP Compare with Zero Group, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 23/35] target/arm: Implement SVE floating-point convert precision, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 24/35] target/arm: Implement SVE floating-point convert to integer, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 25/35] target/arm: Implement SVE floating-point round to integral value, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 27/35] target/arm: Implement SVE MOVPRFX, Richard Henderson, 2018/06/20
- Re: [Qemu-devel] [PATCH v5 27/35] target/arm: Implement SVE MOVPRFX,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 26/35] target/arm: Implement SVE floating-point unary operations, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 28/35] target/arm: Implement SVE floating-point complex add, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 29/35] target/arm: Implement SVE fp complex multiply add, Richard Henderson, 2018/06/20
- [Qemu-devel] [PATCH v5 30/35] target/arm: Pass index to AdvSIMD FCMLA (indexed), Richard Henderson, 2018/06/20