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[Qemu-devel] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4 |
Date: |
Fri, 22 Jun 2018 16:32:24 -0400 |
This both advertises that we support four counters and adds them to the
implementation because the PMU_NUM_COUNTERS macro reads this value from
the PMCR.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 92ebd21..3720239 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1618,7 +1618,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_W, .type = ARM_CP_NOP },
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
- * follow (although we don't actually implement any counters)
+ * follow.
*
* Performance registers fall into three categories:
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
@@ -5234,7 +5234,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL0_RW, .accessfn = pmreg_access,
.type = ARM_CP_IO,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->midr & 0xff000000,
+ /* 4 counters enabled */
+ .resetvalue = (cpu->midr & 0xff000000) | (0x4 << PMCRN_SHIFT),
.writefn = pmcr_write, .raw_writefn = raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- Re: [Qemu-devel] [PATCH v5 01/13] target/arm: Reorganize PMCCNTR accesses, (continued)
- [Qemu-devel] [PATCH v5 02/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 09/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 08/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4,
Aaron Lindsay <=
- [Qemu-devel] [PATCH v5 07/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 11/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO, Aaron Lindsay, 2018/06/22
- [Qemu-devel] [PATCH v5 13/13] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/06/22
- Re: [Qemu-devel] [PATCH v5 00/13] More fully implement ARM PMUv3, Peter Maydell, 2018/06/28