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[Qemu-devel] [RISU PATCH v4 18/22] risu_reginfo_aarch64: left justify re
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [RISU PATCH v4 18/22] risu_reginfo_aarch64: left justify regnums and drop masks |
Date: |
Fri, 22 Jun 2018 15:12:01 +0100 |
Left justification is more pleasing to the eye than the default. We
also drop the masking which isn't needed as we are casting to a
smaller size anyway.
This was split out of Richard's re-factoring work for SVE.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
risu_reginfo_aarch64.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c
index 5da9e39..3ccaf0e 100644
--- a/risu_reginfo_aarch64.c
+++ b/risu_reginfo_aarch64.c
@@ -90,7 +90,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, " faulting insn %08x\n", ri->faulting_insn);
for (i = 0; i < 31; i++) {
- fprintf(f, " X%2d : %016" PRIx64 "\n", i, ri->regs[i]);
+ fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]);
}
fprintf(f, " sp : %016" PRIx64 "\n", ri->sp);
@@ -100,9 +100,9 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, " fpcr : %08x\n", ri->fpcr);
for (i = 0; i < 32; i++) {
- fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i,
+ fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n", i,
(uint64_t) (ri->simd.vregs[i] >> 64),
- (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff));
+ (uint64_t) (ri->simd.vregs[i]));
}
return !ferror(f);
@@ -119,7 +119,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo
*a, FILE * f)
}
for (i = 0; i < 31; i++) {
if (m->regs[i] != a->regs[i]) {
- fprintf(f, " X%2d : %016" PRIx64 " vs %016" PRIx64 "\n",
+ fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n",
i, m->regs[i], a->regs[i]);
}
}
@@ -148,13 +148,13 @@ int reginfo_dump_mismatch(struct reginfo *m, struct
reginfo *a, FILE * f)
for (i = 0; i < 32; i++) {
if (m->simd.vregs[i] != a->simd.vregs[i]) {
- fprintf(f, " V%2d : "
+ fprintf(f, " V%-2d : "
"%016" PRIx64 "%016" PRIx64 " vs "
"%016" PRIx64 "%016" PRIx64 "\n", i,
(uint64_t) (m->simd.vregs[i] >> 64),
- (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff),
+ (uint64_t) m->simd.vregs[i],
(uint64_t) (a->simd.vregs[i] >> 64),
- (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff));
+ (uint64_t) a->simd.vregs[i]);
}
}
--
2.17.1
- [Qemu-devel] [RISU PATCH v4 08/22] risugen: Initialize sve predicates with random data, (continued)
- [Qemu-devel] [RISU PATCH v4 08/22] risugen: Initialize sve predicates with random data, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 09/22] risugen: use fewer insns for aarch64 immediate load, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 10/22] risugen: add reg_plus_imm_pl and reg_plus_imm_vl address helpers, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 11/22] risugen: add dtype_msz address helper, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 22/22] risu_reginfo_aarch64: handle variable VQ, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 14/22] risu: add process_arch_opt, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 16/22] risu_reginfo_aarch64: unionify VFP regs, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 15/22] risu_reginfo_aarch64: drop stray ;, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 18/22] risu_reginfo_aarch64: left justify regnums and drop masks,
Alex Bennée <=
- [Qemu-devel] [RISU PATCH v4 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 17/22] risu_reginfo: introduce reginfo_size(), Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 12/22] contrib/generate_all.sh: allow passing of arguments to risugen, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 19/22] risu_reginfo_aarch64: add support for copying SVE register state, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch, Alex Bennée, 2018/06/22
- [Qemu-devel] [RISU PATCH v4 13/22] risu: move optional args to each architecture, Alex Bennée, 2018/06/22